Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyPowerDynamicPowerDynamic Power +Leakage PowerCABXRoomTemperatureDPower Dissipated byPackageStable OperatingPoint: StableTemperature andLeakage PowerPoint of ThermalRunawayTemperatureFigure 1: Temperature ⇔ Leakage Interdependence(both dynamic and leakage). This increased power dissipationraises the operating temperature which increases the error rate.In the light of these conflicting phenomena, it is imperative toconsider these influencing factors in a unified manner. In thispaper we examine the sensitivity of memory errors to temperatureand observe that an increase in the V dd does not guaranteea reduction in the probability of error because of the effect oftemperature.2 Leakage Aware FloorplanningFloorplanning at the system level is the placement of functionalIP-blocks with uncertain dimensions, but with fixed area. Theobjective of floorplanning is to determine a layout of blockswhile optimizing the total area of the chip and the total wirelength. The following observations motivate our research:1. The subthreshold current (the main component of leakagecurrent) of a transistor has been shown to have a superlineardependency on temperature. For newer technologies,the size of a transistor is even smaller and hence thesensitivity of leakage power due to temperature is evenmore pronounced.2. Different functional blocks have different dynamic powerdissipation profiles and hence produce varying local temperatures.The die temperature for a block in a system-onchip(SoC) is not confined to the block itself and effectsthe temperatures of all its neighboring blocks because ofthermal diffusion. Thus the placement of blocks in theSoC determines the temperatures of the blockThe above observations, when considered together, lead us tobelieve that floorplanning should have an effect on the leakagepower. This motivated us to investigate temperature dependentleakage power-aware floorplanning at the system level. A leakagepower-aware floorplanner considers the dynamic powerprofile of the blocks to calculate the block temperatures usingwhich the leakage power is estimated. The floorplan is thenoptimized for leakage power along with area and wire length.2.1 Power and TemperatureWithin the chip, different regions or different functional blocksin a SoC have different power dissipation. A good rule-ofthumbis that the regions (or the functional blocks in a SoC)with high power densities usually have higher temperatures aswell. But this may not always be true because the heat of ablock is not confined to itself and tends to move from a hightemperature region to a low temperature region, primarily bythe mechanism of conduction. This phenomenon is called thermaldiffusion. The temperature of a particular region in thechip depends on the power densities of the adjacent regionsas well. Hence, the floorplan is a key component when calculatingtemperatures of blocks in a SoC because it determinesthe neighborhood (adjacent blocks) of each block. Koren et al.[1] have shown that power densities do not necessarily map totemperatures because of thermal diffusion. In their results, ablock whose power density was about 5X the power density ofanother block had a lower temperature by about 12 o C.2.2 Temperature ⇔ Leakage InterdependenceWhile the super linear dependency of leakage power on temperatureis well examined, there also exists a positive feedbackloop between temperature and leakage power. In Fig. 1there are two curves: The curve for the total power dissipationwhich includes both dynamic and leakage powers. Unlikeleakage power, the dynamic power is not affected by temperature.The other curve is for the power dissipated by the packageto the environment. The curve shows that the heat dissipatedto the environment by the package increases as its temperatureincreases and angle X represents the quality of package.For initial room temperature, the total power dissipation (PointA) is the sum of non-zero leakage power dissipation (at roomtemperature) from the transistors and the dynamic power. Thepackage must dissipate this power to the environment in theform of heat. Because of this there is an increase in the temperatureof the package to Point B. Due to this elevated temperaturethe leakage power generation increases and the total powerreaches Point C which further appreciates the temperature toD. Thus there is a positive feedback loop between temperatureand leakage power which causes an increase in both of them. Asteady state operating temperature is reached when the powergenerated by the blocks is balanced by the power dissipated bythe cooling mechanisms and package. At this steady state, thetemperature of the package is at a point where it dissipates allthe substrate power dissipation without having to increase itsown temperature. If the power generated becomes greater thanthe capacity of power dissipation by the package, the temperatureswill rise beyond the thermal runaway temperature andthere will be a thermal melt down. This phenomenon has beenvalidated by data from both industrial test facilities and otherpublished works [2], [3].2.3 Leakage Aware FloorplanningFig. 2 describes our leakage aware floorplanning [4]. We haveused slicing tree based simulated annealing floorplanning inour work. We briefly introduce some of the other terminology:total area of the chip is the sum of active area (sum ofthe areas of the transistors of all the blocks) and inactive area(sum of the areas of dead space, interconnects routed betweenthe blocks, and connecting ports of the blocks). A new candidatefloorplan solution is generated by making a random moveon the current floorplan solution. Three types of moves are©EDA Publishing/THERMINIC 2008 38ISBN: 978-2-35500-008-9