Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyMultiscale 3D Thermal Analysis of Analog ICs:from Full-Chip to Device LevelMarek Turowski 1 , Steven Dooley 2 , Ashok Raman 1 , and Matthew Casto 21CFD Research Corporation (CFDRC), 215 Wynn Drive, Huntsville, Alabama 35805, USA2Air Force Research Laboratory (AFRL), Wright-Patterson Air Force Base, Ohio 45433, USAAbstract - We have developed and employed an automatedmulti-scale modeling approach to investigate thermal issues inanalog integrated circuits (ICs) and to enable “thermallyaware” design thereof. Thermal analysis from full-chip scaledown to the single transistor level was made possible with thisapproach utilizing the finite volume three-dimensional (3D)numerical technique. We have developed new methods andtools that import GDSII layout of entire IC and generate 3Dmodel. The tool provides a 3D temperature map that can showthermal gradients across a chip, as well as local temperaturedistribution (hot spots) down to single transistor level. Thisallows introducing temperature back into design process. Ourmethod and tools are demonstrated on a couple of radiofrequency(RF) chips. The multiscale modeling has beenverified with infrared temperature measurements.Key Words - three-dimensional, modeling, simulation, layout,temperature.I. INTRODUCTIONHeat generation in integrated circuits (ICs) and resultingelevated temperatures adversely affect semiconductordevices and circuits in terms of both functional operation andreliability. In analog and radio-frequency (RF) integratedcircuits, the cutoff frequency of transistors rapidly degradeswith increasing temperature due to increased carrierscattering rate [1]. The increasing local power density ofmodern chips and their growing lateral dimensions lead totemperature gradients that affect delays, power, and signalintegrity. The observed trends clearly indicate theimportance of the suppression of the thermal effects,preferably yet during the electrical design process.Our earlier works [2], [3], [4] demonstrated that onlymajor high-thermal-conductivity paths to substrate and heatsink are significant for full-chip scale thermal results. In thiswork, we present our approach and examples of generatingfull-chip 3D thermal model, with automated elimination ofthe minuscule layout elements that do not affect thermalresults. Our new method and tools provide a 3D temperaturemap that can show thermal gradients across a chip, as well aslocal temperature (hot spots) down to single transistor level.The modeling tools have been tested and demonstrated onseveral realistic RF ICs based on a high performance SiGeBiCMOS technology, and verified with infrared temperaturemeasurements.II. 3D MODELING DIRECTLY FROM IC LAYOUTThe thermal simulation is performed using a detailed 3Dfinite volume based solver, CFD-ACE+ [5]. To enableautomated generation of a full-chip 3D model and mesh forthe thermal solver, we have adapted and enhanced theCFDRC Micromesh software [6]. It is used to import the ICdesign layouts (in GDSII formats), create automatically a 3Dmodel from the selected layout part (sub-circuit or full chip),and generate the 3D simulation grid.However, full GDSII layouts of real chips are very largesets of data, containing many thousands or even millions ofelements, including semiconductor active devices, passivedevices, metallic interconnects, vias, bonds, etc. With thesub-micron dimensions in modern ICs, and full-chip sizes ofseveral millimeters, achieving the required resolution of anentire 3D mesh fully including all the IC layout details iscomputationally impossible. This is true even for analog/RFICs, which contain relatively smaller number of elementsthan digital ICs. An example of such situation is illustratedin Figure 1, for one of our test chips (IC1). In order toresolve all details from this GDSII layout, a 3D mesh of thefull chip would require more than 10 16 mesh cells, which istotally impossible to handle by present computational tools.Model Scale: IC1 ≈ 8000 um x 2300 um, IC1 Layout Resolution: 0.01 um=> Needed Mesh Resolution ~ 8e5 (in 1D) !Bump Bond Pads(red)For Official Use OnlyFigure 1. Example an RF IC chip (“IC1”) on a substrate. The size of IC1 isapproximately 8000 μm by 2300 μm, and the GDSII layout elements aredrawn with resolution 0.01 μm – a fully resolved 3D mesh is infeasible.Our works [2], [3] demonstrated that only the major highthermal-conductivitypaths to substrate and heat sink (suchas bonds and thick vias) are significant for full-chip-scalethermal results. In the RF IC cases analyzed here, these mostimportant heat conducting paths to heat sink are the bumpbonds between the flipped (face down) chip and the multi-11©EDA Publishing/THERMINIC 2008 64ISBN: 978-2-35500-008-9