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24-26 September 2008, Rome, ItalyDuring this event, the integrated over-current protection ofthe SPS devices limits the current till the thermal shut downoccurs. The current flowing through the active switch isrecorded by an oscilloscope. The signal In2 for activating theswitch is used as a synchronization pulse to trigger theoscilloscope. The shut down time is read out from thecurrent waveform. For this investigation, samples withdifferent size of die attach voids were selected. The voidcontent in the die attach was determined by ScanningAcoustic Microscope (SAM) where a 2D scan wasperformed from the backside of the sample's package. Theresults are shown in Fig. 7. It is clearly visible that the shutdown time t sd decreases with increasing content of voids.This is in accordance with the simulation results.For certain SPS devices possessing a package and chipsymmetry, this method can be used to determine the tilt ofthe die. A very appropriate candidate to illustrate this is theSPS device analyzed for voids occurrence in the previousanalysis. A sample with a void free die attach was chosen. Inthat device, the shut down time was measured for bothchannels under same conditions as in the previous analysis.Due to the symmetry, if there is no tilt of the die, the shutdown time must be same for both channels. Themeasurement has revealed that the channel 1 of the deviceswitches off earlier than the channel 2 (see Fig. 8). Afterperforming a physical cross-section of the device, it has beenfound out that there is indeed a tilt of the die as shown inFig. 9.Channel 1large thickness and a thinner die attach with small voids. Thesample #1 versus sample #2 illustrate this case. However, thesamples from #3 to #5 containing big voids in the die attachhave much smaller shut down time and therefore it ispossible to find a limit value to sort out the devices with bigvoids, especially if the voids occur close to the integratedtemperature sensor.III.CONCLUSIONS AND DISCUSSIONUsing FEM, a method for detection of die attachimperfections in SPS devices was evaluated. It was shownthat this method can be applied for sorting SPS devices withgood accuracy if the die attach thickness is well controlled inthe soldering process. The practical applicability of themethod was demonstrated on a batch of SPS devices.Further, it was shown that for SPS devices exhibitingpackage and chip symmetry, this method can also be used todetermine the die tilt.Finally, it is necessary to note that for good performanceof this method it is necessary to choose proper operatingconditions, like well-determined power dissipation andambient temperature. To be able to compare a group of SPSdevices, the power dissipation in every device should haveapproximately the same value. The shut down time has to belong enough, so that the heat can diffuse to and through thedie attach and thus can influence the temperature on the diesurface. On the other hand the time should not be too long,otherwise the influence of the die attach will be suppressedby the overall package thermal properties and the influenceof the package environment.Channel 20 20 40 60t sd[ms]Fig. 8 The measured shut down times of the sample #1 for both channels.ACKNOWLEDGMENTAuthors would like to thank D. Metzner, F. Riedl,C. Zych, U. Fröhler and M. Tripolt from InfineonTechnologies, and all our colleagues who have helped torealize this work.This work was jointly funded by the Federal Ministry ofEconomics and Labour of the Republic of Austria (contract98.362/0112-C1/10/2005) and the Carinthian EconomicPromotion Fund (KWF) (contract 98.362/0112-C1/10/2005).(a)HeatsinkFig. 9 Analysis of the die tilt of the sample #1, (a) SAM picture (the dashlineshows the position of the performed physical cross-section),(b) optical picture of the cross-section with height dimensions of the die andthe die attach.As mentioned above when discussing simulation results, ifthe die attach thickness is not well controlled in the solderingprocess, it is difficult to distinguish between a die attach with(b)REFERENCES[1] M. Glavanovics, T. Detzel, K. Weber, “Impact of thermal overloadoperation on wirebond and metallization reliability in Smart PowerDevices,” in Proc. ESSDERC, Leuven, 2004, pp. 273-276.[2] M. Lackner, V. Košel, M. Glavanovics, “Evaluation of ∆VSDMeasuring Method to detect Package Irregularities in Smart PowerSwitches,” in Proc. Austrochip, Graz , 2007, pp. 173-178.[3] B. Murari, F. Bertotti, G.A. Vignola, “Smart Power ICs,” Springer,Germany.[4] William D. Walker, William F. Weldon, “Thermal modeling andexperimentation to determine maximum power capability of SCR’sand,” IEEE Trans. on power electronics, vol. 14, no. 2, March 1999,pp. 316-322.[5] V. Košel, R. Sleik, M. Glavanovics, “Transient non-linear thermalFEM simulations of Smart Power Switches and verification bymeasurements,” in Proc. Therminic, Budapest, 2007, pp. 110-114.©EDA Publishing/THERMINIC 2008 207ISBN: 978-2-35500-008-9