Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, Italythus resulting in the usage of a large fraction of fast cells(i.e., LVT and/or oversized). Experimental results, collectedfor several standard benchmarks and using a state-of-the-art,65nm industrial technology, fully support our claim that thecircuits optimized using our algorithms are never subject totiming violations.We conclude by observing that, conversely from many existingdual-threshold optimization techniques (e.g., [10], [11]), ourapproach to V t assignment does not involve other kinds ofgate/circuit modifications, e.g., gate re-sizing, but it onlyapplies selective cell swapping from LVT to HVT. As such,it can be seen as orthogonal, thus superimposable, to otherleakage optimization solutions, with the purpose of adding tothe final circuit temperature-insensitivity properties.The remainder of the paper is organized as follows. Section IIdescribes in detail the impact that ITD has on circuits operatingat non-constant temperatures, while Section III illustrates theactual inadequacy of standard synthesis of handling ITDinducedeffects, and presents a dual-V t assignment algorithmwhich improves that of [2]. Section IV offers the experimentalvalidation of the fact that our optimization technique originatesrobust, temperature-insensitive circuits with reduced leakageconsumption. Finally, Section V closes the paper.To better understand the relationship between temperaturefluctuations and performance, Equation 4 describes a simpledelay model [12]:D p ∝ C outV dd C out V dd≡(4)I d μ(T )(V dd − V t (T ))where D p is the delay of a standard gate, C out is the outputload capacitance, and V dd is the supply voltage. Thus, adecrease in μ degrades performance, while a decrease in V tmakes the gate faster. The dominant effect is the one thatdefines the resulting trend. For a given V dd ,ifV t is sufficientlysmall, the threshold voltage lowering is negligible comparedto the supply voltage, and the quantity V dd − V t of Equation 4is relatively insensitive to temperature fluctuations; thus themobility effect dominates and the performance degrades astemperature increase. This is the classical assumption uponwhich design flows work today. Conversely, for cells withlarger V t , the thermally-induced threshold voltage variationbecomes a large percentage of V dd , and the denominator ofEquation 4 becomes more sensitive to V t variations; cells becomethus faster as temperature increases, showing an InverseTemperature Dependence. The phenomenons described above1.031.02II. DESIGN IMPACT OF ITDThe propagation delay of an integrated circuit is a function ofthe drain current produced by active transistors, which in turnis determined by a set of device parameters that are sensitive totemperature. By deriving simple relations from the alpha-lawmodel [12], the active drain current of a MOS device (i.e., I on )can be approximated by the following proportional function 1 :1.01LVTNorm. Propagation Delay10.990.980.970.960.95HVTnand3x2LVTnand3x2SVTnand3x2HVTnor2x2LVTnor2x2SVTnor2x2HVTivx2LVTivx2SVTivx2HVTSVTI on ∝ μ(T )(V dd − V t (T )) α (1)where μ is the carrier mobility, V dd is the supply voltage, V tis the threshold-voltage, and α is a positive technological constant.As described by Equation 1, the temperature dependenceof the drain current is embedded in the two device parametersμ, and V t . An analytical expression of these two variables canbe written as:( ) m 300μ(T )=μ(300)(2)TV t (T )=V t (300) − k(T − 300) (3)where 300 is the temperature in Kelvin, and m and k aretechnology constants. As described in Equations 2 and 3,the values of both μ, and V t are lowered as temperatureincreases. Carrier mobility is reduced due to the increaseof scattering effects in the channel surface, while thresholdvoltage is reduced due to Fermi level lowering. However, thedrain current is affected is opposite ways due to the lower ofthese values. As described in Equation 1, a decrease in themobility causes the current to decrease, while a decrease inthreshold voltage causes the current to increase.1 We are considering that both mobility and saturation velocity show a temperaturedependence close to each other; in this sense, considering only the mobility effect is areasonable approximation [9].Fig. 1.0.9420 40 60 80 100 120 140Temperature [° C]Propagation Delay vs. Temperature for a Subset of Standard Cells.are illustrated in Figure II, where a subset of minimum sizedcells belonging to a commercial 65nm standard library areconsidered: 3-input NAND (nand3x2), 2-input NOR (nor2x2),and INVERTER (ivx2). The plot shows the normalized propagationdelay of the gates as a function of the temperaturefor three different threshold voltages (low-V t (LVT), standard-V t (SVT), and high-V t (HVT)). The characterization wasmade for V dd of 1V, which is the nominal value for thereference technology, and an equivalent load capacitance offan-out 1. For a smaller threshold voltage (LVT-lines), themobility effect dominates and the propagation delays increasewith temperature (around 3% of degradation for 100 ◦ C oftemperature swing). In contrast, for the HVT cases, the cellsare more sensitive to threshold voltage lowering, and weobserve a 4% of performance improvement from 25 ◦ C to125 ◦ C (ITD). A different behavior can be seen for standardV t gates (SVT-lines). In this case, the SVT gates may showa non-monotonic dependence. At lower temperatures, themobility effect dominates (delay degradation), while, at hightemperatures (higher than 80 ◦ C), the V t dependence makes thegates faster. Similar temperature dependence could be shownfor other standard gates. The magnitude of these variations are©EDA Publishing/THERMINIC 2008 32ISBN: 978-2-35500-008-9