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After having determined the k eff value for the selected(repetitive) fragment of IC layout, we must decide whichGDSII layer mask (number, N eff ) has the best geometry torepresent the layers (blocks) to be replaced by “k eff -blocks”.Once the appropriate GDSII layer is selected, we use thefiltering function in the CFDRC Micromesh tool to replaceall the original, thin metallic interconnects and via layers bythe corresponding “k eff -blocks”. This is illustrated in Figure3. As indicated there, with all the small vias andinterconnects in the top part, just for one bump bond, adetailed 3D model would generate mesh of about 2.4 millioncells (> 4 × 590K). By replacing those sections with k eff -blocks, the 3D mesh size goes down to 2K cells, that is over1000 times smaller!Anisotropic Effective Thermal ConductivityWe have also analyzed the effects of anisotropic effectivethermal conductivity, and the needs of using it for 3D ICthermal modeling. To calculate the directional componentsof k eff in the lateral (X, Y) directions, we applied a similarapproach as in previous section (Figure 4), but this time theheat source plane and isothermal BC plane were applied toside walls of a selected layout section (3D model).After having calculated the lateral k eff,X and k eff,Ycomponents, we performed several numerical experiments tofind out the effects of anisotropic thermal conductivityversus standard isotropic k eff . It has appeared that only thevertical (Z) component of k eff is critical for the resultingtemperature in the silicon part of IC. As a results of theseexperiments, we concluded there was no need to use theanisotropic k eff for the IC structures with forests of vias,because the vertical (Z) k eff component was dominating andultimately determining the T results.V. CLEANING THE LAYOUT FOR FULL-CHIP 3D MODELAnother feature of modern IC designs that causesproblems for automated generation of 3D meshed thermalmodel from GDSII layout is the presence of large arrays ofsmall metallic filling elements (“fillers”) used to improvemechanical properties of the wafer, for IC processing steps,such as chemical mechanical polishing (CMP). These arevery small elements, normally also present in GDSII layoutdescription, but they have very little, if any, effect on thetemperature distribution on the full-chip scale, mostlybecause these elements (even if metallic) are isolated fromeach other by the inter-metal dielectric that is also a goodthermal insulator. Example of such a situation is presented inFigure 5. The presence of thousands of very small metallicelements is a major obstacle for generation of appropriatelycoarse 3D mesh for the full-chip scale thermal model.To enable automated generation of a full-chip 3D meshedthermal model, we also enhanced the CFDRC Micromeshtool with the new capability of removing from any selectedlayer of imported GDSII layout, all the layout elements ofselected dimensions (in particular, e.g. smaller than userdefinedlimits, in any direction). This new capability allowedus to clean up the full-chip layout imported from GDSII file,and remove all the very small elements not important forthermal results.24-26 September 2008, Rome, ItalyBump Bond Pads(important for T)Many small elements – not important for Thermal results… can be removed from 3D modelFigure 5. RF IC layout – thick metal layer – with large arrays of smallmetallic elements, which cause problems for automated 3D thermalmodeling from GDSII layout.VI. HEAT SOURCES FOR THE FULL-CHIP MODELCreating a 3D thermal model of entire IC requires also aspecial approach to determining heat sources: their positions,method of extracting from GDSII layout, and calculation ofthe value of power dissipated in each source. For analog / RFintegrated circuits in BiCMOS technologies, we assumedthat the heat is mainly generated in the active devices, whichare bipolar junction transistors (BJT) or heterojunctionbipolar transistors (HBT). Similarly to [7], a uniform heatgeneration was assumed in the collector-base (C-B)depletion region. To locate the heat sources within the entireIC layout, we identify and select the layout elements thatcorrespond to C-B junctions of all the BJTs or HBTs, usingautomated processing of the imported GDSII layout.Additional new features that we have recently added toour Micromesh tool, utilizing Python scripting, allow forautomated selection of the C-B junction layer from theimported GDSII layout, identification of all BJT/HBTdevices, calculation of their C-B junction areas, and finallydetermination of average dissipated power, in W/m 2 , foreach C-B junction as a heat source. The calculated powerdensity value is then easily applied to all the heat sourcesthrough the graphical user interface (GUI) of the CFD-ACE+ solver.In our example chip, IC1, there are about 70 HBT devices,which are sparsely located throughout the chip. After havingdivided the total dissipated power of the chip by the surfacearea of all the combined C-B junctions, the calculatedaverage power density was 7.9×10 7 W/m 2 . This value wasused for subsequent thermal simulation of IC1.VII. FULL CHIP 3D MODEL AND MESHUsing the newly developed GDSII importing/filteringcapabilities of Micromesh, we were able to generate a full3D geometrical model of entire chip, including all theelements important for the thermal characteristics of the IC.Such a model is presented in Figure 6.©EDA Publishing/THERMINIC 2008 66ISBN: 978-2-35500-008-9