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24-26 September 2008, Rome, ItalyIII.SIMULATION AND ANALYSIS FLOW AND VALIDATIONA. Simulation and Analysis FlowTo sum up above steps, Fig. 8 shows an overview of thesimulation and analysis flow:A. Select an inverter with suitable transistor size as aunit inverter, and then establish an inverter chain asthe test circuit to imitate a real logic path.B. Obtain simulated values of delay d abs with differentvalues of fanout h through the test circuit. Thenevaluate the simulated values of τ, g, and p by theequation d abs =τ(gh+p) and the curves of d abs vs. hunder different temperature and voltage conditions.C. Simulate with a unit inverter, give input 0 and 1, andthen obtain the average value of C in under differenttemperature and voltage conditions.D. Simulate with each PMOS and NMOS transistor,and obtain the values of saturation current I d andthreshold voltage V t under different temperature andvoltage conditions.E. Use the data received from above steps, calculatethe values of equation 1/g=(m t t+b t )V DD +C, andobtain the calculated values of g.F. Compare the calculated values of g with simulatedvalues, then, we can prove that the proposedextended model is accurate enough.Fig. 8. An overview of the simulation and analysis flow.B. ValidationFig. 9 shows the comparison between simulated andcalculated values of 1/g in 3-D chart. The calculated value ofg is obtained from (14). After validation, the accuracy of thissimple extended logical effort model can achieve about 90%.IV. CONCLUSIONThe traditional logical effort delay model may not estimatelogic path delay correctly while temperature and supplyvoltage changing. Thus we present a simple extended logicaleffort model to support for temperature and voltage variations.The linear characteristic is convenient for designers toquickly estimate logic path delay and optimize an N-stagelogic network, and the integration of proposed model andCAD tools is easier. Combining the proposed extendedlogical effort model with existing thermal simulators, theutility of the proposed model can be fulfilled. The simulationand analysis flow is established and the validation of theproposed model is shown in Section III. After validation, theaccuracy of this new extended logical effort model canachieve about 90%.ACKNOWLEDGMENTThis research is supported by Biomimetic SystemsResearch Center, NCTU and National Science Council,Taiwan. The contract numbers are NSC 96-2220-E-009-017and NSC 97-2220-E-009-005. The simulation tools aresupported by National Chip Implementation Center, Taiwan.Fig. 9. The comparison between simulated and calculated value of 1/g in 3-D.Simulated values are solid lines and calculated values are dotted lines.REFERENCES[1] I. Sutherland, B. Sproull, and D. Harris, Logical Effort: DesigningFast CMOS Circuits. San Francisco, CA: Morgan Kaufmann, 1999.[2] X. Y. Yu, V. G. Oklobdzija, and W. W. Walker, “Application oflogical effort on design of arithmetic blocks,” Conference Record ofthe Thirty-Fifth Asilomar Conference on Signals, Systems andComputers, vol.1, pp. 872–874, 2001.[3] A. Kabbani, D. Al-Khalili, and A.J. Al-Khalili, “Delay macromodeling of CMOS gates using modified logical effort technique,”IEEE International Conference on Semiconductor Electronics, pp.56-60, December 2004.[4] B. Lasbouygues, S. Engels, R. Wilson, P. Maurine, N. Azemard, andD. Auvergne, “Logical effort model extension to propagation delayrepresentation,” IEEE Trans. on Computer-Aided Design ofIntegrated Circuits and Systems, vol. 25, no. 9, pp. 1677-1684,September 2006.[5] W. M. Chan, “A comprehensive thermal-aware power managementsystem with block-level optimization in 100nm CMOS technology,”Master Thesis, National Chiao Tung University, 2005.[6] N. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits andSystems Perspective, 3rd edition. Boston, MA: Addison Wesley,2004.[7] T. Sakurai and A. R. Newton, “Alpha-power model and itsapplications to CMOS inverter delay and other formulas,” IEEE J.Solid-State Circuits, vol.25, pp. 584-594, April 1990.©EDA Publishing/THERMINIC 2008 88ISBN: 978-2-35500-008-9