Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, Italypropagation delay actually increases with temperature (directtemperature-dependence).In this case the worst-case delayoccurs at the highest temperature. Finally, if the HVT cellsdominate, the derivative is negative, and the path gets fasteras temperature increases (inverted-temperature-dependence).This is the case in which the actual worst delay occurs atminimum temperature. In all three cases, the propagation delayis linear with respect to temperature, and timing compliancecan be simply checked at the two boundaries of the operatingtemperature range.III. TEMPERATURE-AWARE DUAL-V t ASSIGNMENTFig. 3. Graph depicting the solution space of our synthesis tool.To better understand the limits of standard synthesis approachesand motivate our solution, Figure 3 illustrates the{delay, leakage} design space of the dual-V t assignmentproblem. For a given circuit netlist, where logic function andsize of the gates are fixed, each possible threshold voltageconfiguration can be represented as a coordinate point (Delay,Leakage).For instance, the all-LVT and all-HVT points indicate thecoordinate of a netlist mapped with only LVT or only HVTcells respectively. While the circuit made up of LVT cellsshows the minimum delay and the maximum leakage power(coordinate D min ,L max ), the all-HVT solution minimizes thestatic power consumption at the cost of performance (coordinateD max ,L min ). These two points delimit the feasiblesolution space. Due to temperature fluctuations, the delaycoordinate of the solutions can move horizontally (in the plotthis variation is indicated as a horizontal line emanating fromthe point of interest). In the case of an all-LVT solution, sincethere is a direct temperature dependence, the delay increaseswith temperature, and the point moves to the right side (lineemanating from point D min ,L max ). For the case of an all-HVT solution, the inverted temperature dependence makes thecircuit slower at room-temperature, and the point moves to theleft side (line emanating from point D max ,L min ).Let D nom be the delay constraint specified by the designer;only the portion of the feasible area to the left of D nom isthe one of interest.Since commercial multi-V t synthesis toolstypically assume worst case conditions to be at the highestallowable operating temperature (i.e., T max ), the delay ofthe synthesized circuit may be within the specified D nomoperating point at this boundary condition of T max , but thereis no guarantee that this nominal delay is satisfied for the entirerange of allowable operating temperatures. Figure 3 with theblue circle of coordinates (D 1 ,L 1 ) in the center of the graph.When the circuit operates at a temperature other than T max ,due to ITD, the point shifts beyond D nom in the unfeasibleregion.Knowing that inverted temperature dependence exists, a designermight try to compensate for the ITD effect by overconstrainingthe synthesis of the circuit with a delay less thanD nom . The resulting solution is plotted in Figure 3 with thepoint of coordinates (D 2 ,L 2 ). In this case, even if the pathdelays increase for temperatures other than T max , the delaystill remains in the feasible green area, and the global delayconstraint is met. However, as side effect, the over-constrainedapproach tends to generate circuits that are shallower andwider, thereby consuming more area and leakage power (L 2 >L 1 ).In contrast to the above over-constrained approach, ourmethodology takes into account the temperature inversioneffect as part of the dual-V t synthesis process, obtaining anetlist that is compliant with the nominal timing constraint atthe boundaries of the temperature range (where timing faultcan appear). In effect, we exploit the slack provided by theover-constrained circuit, assigning higher threshold voltagesto the gates which show a larger leakage, and simultaneouslychecking the timing compliance at the two boundaries of theoperating temperature range. The result is shown in Figure 3,where the point of coordinates (D 3 ,L 3 ) indicates our solution.Since we consider the two potential worst-case temperaturesduring the V t assignment process, the resulting solution canonly correspond to a time interval included in the feasiblegreen area, showing a leakage coordinate which is quitesmaller compared to the over-constrained solution (L 3