Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyWLBLTSLPLNLLVddRPRNRSRFigure 3: SRAM celltion schemes such as the Viterbi Algorithm [5]. But these errorcorrecting mechanisms consume large amount of power andthere is an intrinsic trade-off between the power consumptionand the error resiliency of a design. Temperature increases thecell switching delay which causes the probability of errors in amemory to increase [7].Classically, failures in embedded memory cells are categorizedas either of a transient nature (because of operating conditions)or of a fixed nature (due to manufacturing errors). Failuresmanifest as 1) Increase in cell access time, or 2) unstableread/write operations. In sub 100nm design, Random DopantFluctuation (RDF) has the dominant impact on the transistorsstrength mismatch and is the most noticeable type of intra-dievariation that can lead to cell instability and failure in embeddedmemories. RDF has a detrimental effect on transistors thatare co-located within one cell, by creating a mismatch in theirintrinsic threshold voltage, V t . Furthermore, these effects are astrong function of the operating conditions (voltage, frequency,temperature etc.)Figure 3 shows the typical six-transistor cell used for CMOSSRAM. During the read operation, the read time, T Read is verysensitive to the variations in the threshold voltages of the accesstransistors(S R/L ) and the pull-down transistors (N R/L ).Whereas during the write operation, variations in the thresholdvoltages of the access transistor and the pull-up (P R/L )transistor have the strongest effect on the write time, T Write .In order to calculate the probability of failure, we considered±6σ tX variation for the threshold voltage of S R/L , N R/L andP R/L based on the gaussian distribution of RDF effects. Thenwe measured the read time (T Read ), write time (T Write )andthe voltage at the storage node (V R/L ) for each (V dd )andtemperature. If T Max is the maximum allowed time we calculatethe cell failure probability as following: Read failure(T Read >T Max ), Write failure (T Write >T Max ), and Destructiveread failure: An increase in the storage node voltagesuch that V R/L >V Trip where V Trip is the trip voltage of theinverter in the SRAM (the value stored in the cell will flip).3.1 Factors Influencing Memory ReliabilityFig. 4 shows how errors in memory are affected by differentparameters. As the operating frequency is increased theprobability of memory errors increase ( 1○) because it enforcestighter bounds on the time allowance for memory accesses. Increasein V dd reduces the cell delay and thus causes the errorsto decrease ( 2○). The errors in memories increase along withthe rise in temperature ( 3○) because of increase in the cell delay.These are not the only relationships that effect memoryBLC4DynamicPowerDynamicPower+fFrequency(Memory Speed)Pe1f7Power++8 9Leakage ++ Power65TPeVdd+VddTemperaturePeVdd+ +Probability ofErrors in Memoryf2Vdd3VddTPeFigure 4: Sensitivity of Memory Errors0Steady StateTemperatureerrors. From Fig. 4 we also examine other interrelationships atwork. The dynamic power dissipation in memory cell increaseswith increase in both frequency (∝ f)( 4○) andV dd (∝ Vdd 2 )( 5○). The leakage power, on the other hand, increases with V dd(∝ e βV dd,β > 1) (6○). Both dynamic power ( 7○) and leakagepower ( 8○) dissipation determine the operating temperature.Leakage power dissipation of a cell is known to increasesuper-linearly with increase in temperature. As temperatureincreases, the leakage power dissipation increases ( 9○) whichfurther elevates the temperature. This ‘positive feedback loop’between temperature and leakage power stabilizes when steadystate operating temperatures have been reached ( 0○) atwhichstate all the dynamic and leakage power dissipation is transferredto the environment by the package. Thus the list ofparameters that effect the probability of errors in memory isas follows: V dd , frequency, temperature, leakage power, anddynamic power. A comprehensive approach to memory/logicdesign must consider these relationships.Conventionally, designers increase the supply voltage V dd toincrease the reliability of the memories (reduce the probabilityof errors). But an increase in V dd also increases the dynamicpower dissipation of the memory cell which raises the temperatureof the memory. Thus there are two conflicting phenomena:increase in V dd which reduces memory errors andincrease in temperature which increases memory errors. In thispaper we quantify the effect of temperature on the probabilityof failures in memories.4 Results: Floorplanning for LeakageWe applied our floorplanner on eight industrial SoC designsfrom Freescale Semiconductor’s PowerQUICC family ofSoCs. The influence of leakage power on the floorplanningcan be adjusted using the weight of leakage power (W Leakage )from Eqn. (1). For a higher value of W Leakage , the outputfloorplans are expected to have less leakage but their area andthe wire length increase. For all the results that we present inT©EDA Publishing/THERMINIC 2008 40ISBN: 978-2-35500-008-9