Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, Italyfrom hot to cold (fall time) or from cold to hot (rise time)2,2should not exceed 5 seconds. The dwell time should not beless than 10 minutes and the load should reach the specified2,0temperature within 1 minute. The TST cold is between –25 0 C and (T amb ) while the TST hot varies from (T amb ) to75 0 1,8C. For TCT, the total transfer time should not be less than5 minutes (ramp: 30 0 C /min). For HTSL, the temperaturestorage is 150 0 1,6C for 1000 hours in the thermal chamber(SUN SYSTEM EC11). Various conditions are investigated1,4(Table 1) in order to establish an unequivocal conclusion onthe comparison of the different tests (TST and TCT with and1,2without DC bias, HVD, HTSL, different (Ids) and extremestemperatures ∆T values, TST cold and hot).TABLE ISUMMARY OF THE VARIOUS TESTS CONDITIONS WITH THE SAME CYCLENUMBER (10) AND DWELL TIMES (10MIN)R ds_on[ Ohms ]Befor ageingAfter TCT without DC biasAfter HVDAfter TCT at I ds= 3mAAfter TCT at I ds= 6mA1,04 5 6 7 8 9 10V g s[ V ]Fig. 1. Evolution of the Rds_on after ageing at various Ids values,with Vds=10mVTest Temperatures ∆T I ds at T ambTST hot T amb / +75 0 C 50 0 C 3 mATST cold T amb / -25 0 C 50 0 C 3 mATST-75 0 C / +150 0 C 225 0 C-75 0 C / +75 0 C 150 0 C3 mAWithout DCTCT -75 0 C / +75 0 C 150 0 C bias3 mA6 mAHVD T amb -- 3 mAHTSL 150 0 C --Without DCbiasIV.COMPARISON AND RESULTS DISCUSSIONThe device transconductance G m shift is positive. Fig. 2shows an extrapolation of the transfer characteristic forV gs =[0V,6V] and V ds =10mV. The shift is more important inthe TST cold than in the TST hot one. For instance, at –1.5Vbias the C gd shift is 1.09pF in TST cold (drift 42%) but it is1.52pF in TST hot (20%), see Fig. 3. According to the testedsamples, no results disappearances are observed. To ourknowledge, no equivalent results have been reported in theliterature [9]. HTSL seems to be slower than other ageingtests with these conditions (150 0 C-1000h). Tests in progressat higher temperatures (superior to 150 0 C) and longer times(more than 1000h) should induce more degradationmechanisms.4,5The results obtained highlight shifts of critical electricparameters, which are monitored after accelerated ageingtests.The rise of R ds_on obtained by an output characteristicextrapolation (V ds = [0V; 2V] and V gs = [4V; 10V]) could becorrelated to a decrease of channel current Ids value. Fig. 1also shows the Rds_on evolution with various values ofquiescent current Ids. We notice that TCT without DC biasseems to be slower than TCT with DC bias. Therefore, theincrease of this current and the correlation of thermal andelectrical stresses accelerate the parameter shifts. The R ds_onat 10V gate-source bias is increased from 1.14 Ohms to 1.25Ohms in TCT with quiescent current Ids equal to 3mA,indicating a shift by 9% which increases to 14% with currentequal to 6mA.G m[ 10 -6 S ]4,03,53,02,52,01,51,00,5After TST hotBefor ageingAfter TST cold0,01 2 3 4 5V gs[ V ]Fig. 2. G m Evolution at various ageing conditions, with V ds =10mVThe proposed degradation mechanism consists of hotcarrier generating interface states (traps) and trappedelectron charge which results in a build up of negativecharge at the Si-SiO 2 interface as explained in [8]. Thelocation of this charge is likely to be in the vicinity of theintersection of the impact ionization with the Si-SiO 2interface. This negative charge attracts holes depleting thecharge in the LDMOS n-drift region and increasing the R ds_ondevice resistance.The feedback capacitance Crss is composed of two parts,the oxide capacitance (C OX ) and the drift region capacitance(C SI ). The Crss is then defined by the series combination ofC OX and C SI , and the mathematic relation is given by thefollowing [10]:CrssC×+COX SI= (1)COXCSI©EDA Publishing/THERMINIC 2008 124ISBN: 978-2-35500-008-9