Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyFigure 14 is the whole chip thermal image with a 5Xresolution. From this image, it is shown that the max ∆T =4.9°C in A3, which is a 4 finger buffer amplifier. Figure 15shows a maximum ∆T ≈ 4.9°C across the fingers of A3 witha DC bias. When including the RF signal drive, the max ∆T= 5.3°C, showing RF has a minimal impact on deviceFigure 13. Radiance plot of flip chipped package.temperature.The Thermal Mapper software enables a line probe acrossA3 A2 A1the transistor fingers, which is shown in Figure 15. The max∆T = 3.2°C for the IC1 thermal model, which is in very closeagreement to the thermal image. This validates ourmethodology used to model RF integrated circuits.∆ Tmax= 4.9°C ∆ Tmax= 4.1°C ∆ Tmax= 4.2°CX. CONCLUSIONSFigure 14. IC1 full chip thermal image at 5X resolution. The points ofmaximum temperature ∆T over heat sink (hot spots) are marked. We have described a modeling approach and new softwaretools enabling RF IC thermal simulation and analysis, fromthe full-chip scale down to the single transistor (finger) level.The 3D thermal solution is obtained using the finite volumethree-dimensional numerical technique. Our new tools canimport GDSII layout of entire IC and, for the purpose ofgenerating full-chip 3D thermal model, automaticallyeliminate the layout elements not important for IC thermalcharacteristics, or replace them by effective thermalconductivity volumes. Using this approach, we were able toobtain full-chip 3D models and 3D computational meshesthat are possible to solve on a single PC.We have presented examples of using equivalent thermalconductivity blocks in place of "forest of vias" typical inmodern ICs. Our new methods and tools have beendemonstrated on two different RF IC chips based on a highperformance SiGe BiCMOS technology. The multi-scalethermal modeling has been validated and verified withinfrared temperature measurements.The presented models and simulation results provide 3Dtemperature maps that can show thermal gradients across achip, as well as local temperature distribution (hot spots)down to single transistor level. This allows introducingtemperature information early into design process.Figure 15. A3 radiance (top) and IR measured temperature plot image at15X resolution. A line probe across the transistor fingers is shown at thebottom.REFERENCES[1] J.S. Rieh, et al., “Structure optimization of trench-isolated SiGeHBTs for simultaneous improvements in thermal and electricalperformances,” IEEE Trans. Electron Devices, vol. 52, pp. 2744-2752, Dec. 2005.[2] P. Wilkerson, A. Raman, and M. Turowski, “Fast, AutomatedThermal Simulation of Three-Dimensional Integrated Circuits”,ITherm 2004, Las Vegas, Nevada, June 2004.[3] A. Raman, M. Turowski, and M. Mar, "Layout-based Full ChipThermal Simulations of Stacked 3D Integrated Circuits", Int.Congress IMECE 2003, Washington, DC, paper # EPP-41135.[4] M. Turowski, A. Raman, and M. Mar, “Full-chip 3D ThermalSimulation of Stacked IC’s”, Int. Conf. on Thermal Problems inElectronics, MicroTherm-2003, Lodz, Poland, July 2003.[5] http://www.cfdrc.com/serv_prod/cfd_multiphysics/software/ace/[6] Z. Tan, M. Furmanczyk, M. Turowski, and A. Przekwas, "CFD-Micromesh: A Fast Geometrical Modeling and Mesh GenerationTool for 3D Microsystem Simulations", Int. Conf. MSM 2000, SanDiego, California, March 27-29, 2000, pp.712-715.[7] A. Pacelli, P. Palestri, and M. Mastrapasqua, “Physics-Based andCompact Models for Self-Heating in High-Speed Bipolar IntegratedCircuits”, MSM-Nanotech 2002, Vol. 1, pp. 616 – 619.[8] Infrascope Thermal Mapper Users Manual, Quantum FocusInstruments. Vista, California, 2006©EDA Publishing/THERMINIC 2008 69ISBN: 978-2-35500-008-9