Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyReverse current (A)1.0E-039.0E-048.0E-047.0E-046.0E-045.0E-044.0E-043.0E-04Planar junction (Fig.1a,b)low density of g-r centresPlane junction(Fig.1c,d) high densityof g-r centres150 o C200 o C22 o Ccharacteristic to cause failure.Analysis of failed devices has indicated excessive highreverse leakage current at low voltage and room temperature.The location of excessive high current flow was found at thejunction peripheral surface in a small region of materialdamage with a size of 0.1 - 0.2 mm. If this spot of materialdamage is removed by selective etching, then the blockingelectric characteristic is restored but at higher level of I R thanthe initial one. In Fig 3, the location of the spot of materialdegradation on the peripheral region of the silicon die isshown.Oxide passivation dielectric layer2.0E-041.0E-040.0E+002.5E-03150 o C175 o C0 500 1000 1500Reverse voltage (V)a)Planar junction (Figs.1a,b)low density of g-r centresReverse current (A)2.0E-031.5E-031.0E-035.0E-04175 o C225 o CPlane junction (Fig. 1c,d) highdensity of g-r centres22 oCSpot of material degradationa)Glass passivation dielectricl0.0E+000 500 1000 1500Reverse voltage (V)b)Fig. 2. Reverse electrical characteristics at room and high temperature forPN junctions from commercial silicon diodes ; a) up to 1 mA leakagecurrent level b) above 1 mA(the limit for linear variation) then the electrical characteristicis stable for long time. At 175 o C stability of electricalcharacteristic was observed for the planar diode if the appliedvoltage is 1200 -1400 V but at 200 o C stability was observedonly up to 1200 V. At 225 o C stability was observed only up500 -600 V. The same behavior was observed for the planejunction diode at 175 o C. Finally, 1000 V was applied for theplanar diode at 225 o C and 1000 V for the plane junction diodeat 175 o C with enough time, so that instability of the electricalSpot of material degradation afterb)Fig. 3. Top view of silicon diode dice after failure released from package;a) planar junction diode (Fig. 1a,b) b) plane junction diode (Fig.1c,d)©EDA Publishing/THERMINIC 2008 144ISBN: 978-2-35500-008-9