Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyThe dependence of static power on process variation ismodeled using separate static power equations for typical andcounted, in this case by the first-stage multiplexer of the lookuptable (LUT) shown in Fig. 3.worst-case devices.A= B=0B. Dinamic Power ModelsDynamic power is the additional power consumed throughdevice operation caused by signals toggling and capacitiveloads charging and discharging. The main variables affectingdynamic power are capacitance charging, supply voltage, andclock frequency:⎡12⎤P = CV Q V f ⋅ activitydynamic ⎢ +ShortCircuit⎥⎣2⎦It is important to predict accurately the dynamic powerconsumption of a design. Unsophisticated power analysistools simply model each circuit as a lumped capacitance.C. Simulation-Based Dynamic Power ModelsSimulation-based dynamic power models are used to modelblocks on the device which are highly configurable, such aslogic element (LE) at Altera or configurable logic block(CLB) at Xilinx. It would be useless to cover all the possibleconfigurations of these blocks with measure patterns. Easierto broke up the block into sub-blocks, each with a smallnumber of supported configurations. The detailed blockpower model is developed by simulating every configurationof each sub-block and modeling the resource as a network ofthese sub-blocks.Unsophisticated power analysis tools counts each block asa simple black box where only input and output transitions aremeasured. It is better to measure each block’s internaltransitions. For example, if the input of a simple register istoggled and the clock held high, as shown in Fig. 1, a blackbox model would simply assume that because the output doesnot toggle, no power is consumed.Fig. 1. Simple registerHowever the prediction of the consumed power in internalnodes can be done by modeling the register’s entire internalstructure, as shown in Fig. 2.Fig. 2. Internal toggling of registerAnother example is a simple 2-input AND gatefunctionality that can be implemented in one logic block. Ifone input is held low and another input toggles, a black boxmodel would assume that no power is consumed because theoutput does not toggle. However, a simulation based modelconsider every internal multiplexer, buffer, and wire in theblock, so power consumed by internal toggles is correctly0001Fig. 3. Internal toggling of AND gateD. Routing Power ModelA significant portion of total dynamic power is consumedin the programmable routing fabric of the FPGAs. Dynamicrouting power has two main components: short-circuit currentand power dissipated in charging and discharging loadcapacitances. Fig. 4 illustrates how power is consumed whenan inverter switches a capacitive load.Fig. 4. Power consumed in an inverterFor FPGA routing switches, the load is the lumpedcapacitance, including the metal capacitance of the wire andother interconnect, and the input capacitances of multiplexersand gates that listen to the wire. The input capacitance of eachmultiplexer is determined by its configuration. A transistorlevelmodel of each listening multiplexer has to be used toaccurately calculate its input capacitance based onconfiguration and type.The metal capacitance of the wire is determined by itslength, thickness, separation from its neighbors, and the metallayer where it is implemented. Only the FPGA vendors have adatabase with the precise capacitance of every routing wire onthe device for use in power and timing analysis. Thesecapacitances have to be extracted from device layouts.For most circuits, charging load capacitances is thedominant component of dynamic power. However, the FPGArouting fabric uses large inverters to drive long interconnectlines. These drivers can conduct significant short-circuitcurrents, so this effect cannot be ignored.Short-circuit current occurs because switching signalscannot transition instantaneously, they have non-zero rise andfall times. During the transition, the pull-up and pull-downtransistors of the inverter are both turned on for a period oftime. Current flows directly from the supply to ground and isdissipated in the NMOS and PMOS transistors. Fig. 5 showsthe state of a switching inverter when its input is crossingthrough the half-supply point.00©EDA Publishing/THERMINIC 2008 149ISBN: 978-2-35500-008-9