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24-26 September 2008, Rome, Italycircuits, where most of the power consumed is dissipated in Ideally, the delay variation of the programmable delaynon-arithmetic components like multiplexers, registers, vector element will scale with the delay variation of the FPGAlogic operators, etc.routing resources.The delay insertion technique minimizes glitching in fixedlogic implementations by aligning the input arrival times ofgates using fixed delay elements. This is similar technique to[5] just targets FPGAs. Aligning edges in an FPGA isconsiderably more complex than in an ASIC, since in anFPGA, the required delay times are not known when the chipis fabricated. This means the delays must be programmable. Ifthe delays not managed carefully, the overhead in theseprogrammable delay elements can consume more power thanany savings obtained by removing glitches. [6]V. PROPOSED POWER MODELThe proposed technique involves adding programmabledelay elements within the logic blocks of the FPGA. Withineach logic block, the early-arriving signals have to be delayedso as to align the edges on each LUT input. In this way thenumber of glitches will be reducing on the output of eachLUT. The technique is shown in Fig. 8. By delaying input c,the output glitch can be eliminated. Since only the earlyarrivinginputs are delayed, the overall critical path of thecircuit is not increased.01101110 abc(a) Original circuit with glitch0 ab1cΔ(b) Glitch removed by inserting delayFig. 8. Removing glitches by delaying early-arriving signalsFig. 9 illustrates the programmable delay elements used inthe FPGA logic blocks [6]. The circuit is composed of twoinverters. The first inverter has programmable pull-up andpull-down resistors to control the delay of the circuit. Thesecond inverter has large channel lengths to minimize shortcircuitpower. The pull-up and pull-down resistors each haven stages with a resistor and a bypass transistor controlled byan SRAM bit. The first stage has a resistance of R and theresistance of the subsequent stages is doubled for each stage.Using the control bits, this circuit can be programmed toproduce any delaynΔ ∈{ k, τ + k,2τ+ k,3τ+ k,..., ( 2 − k) τ + k},where τ is the delay produced by a resistance R to charge ordischarge the capacitor C and k is the delay produced by thebypass resistances and the inverters.The delay of the programmable delay element is affectedby temperature, supply noise, and process variation. Althoughnot detailed in this paper, these factors are important sinceadding more delay than necessary may affect the critical-pathdelay of the implementation and not adding enough delay willreduces the amount of glitching that can be eliminated.dd1011Fig. 9. Programmable delay elementVI. CONCLUSIONIn this paper the main requirements and methods for FPGApower model are written. It is considered that the glitching isone of the main contributors of the dynamic powerdissipation. For decreasing it a new glitch minimizationtechnique is proposed. It is using added programmable delayelements within the logic blocks of the FPGA to align theedges on each LUT input and filter out existing glitches,thereby reducing the number of glitches on the output of eachLUT. This will cause less power dissipation of the circuit.The trade-off is that there is area and speed overhead became.As only the early-arriving signals are delayed, there is nosignificant impact on circuit speed (other than increasedparasitic capacitances).In the future the validation of the power model is plannedon various FPGA devices and designs.REFERENCES[1] Bryce Leung, Jeffrey Chromczak, Jennifer Farrugia, “FPGA PowerManagement and Modeling Techniques”, Altera White Paper,WP-01044-1.0, 2007[2] José C. Monteiro, Arlindo L. Oliveira, “Finite state machinedecomposition for low power”, Proceedings of the 35th conference onDesign Automation, pp. 758-763, 1998[3] Daehong Kim, Kiyoung Choi, “Power-conscious High Level SynthesisUsing Loop Folding”, Proceedings of the 34th conference on DesignAutomation, pp. 441, 1997[4] L. Benini, G. De Micheli, A. Macii, E. Macii, M. Poncino, R. Scarsi,“Glitch power minimization by selective gate freezing”, IEEETransactions on Very Large Scale Integration Systems, vol. 8, pp. 287-298, 2000[5] Anand Raghunathan, Sujit Dey, Niraj K. Jha, “Register-transfer levelestimation techniques for switching activity and power consumption”,pp. 158-165, Proceedings of the IEEE/ACM international conferenceon Computer-aided design, 1996[6] Julien Lamoureux, Guy G. Lemieux, Steven J. E.. Wilton, “GlitchLess:An active glitch minimization technique for FPGAs”, pp. 156-165,Proceedings of the ACM/SIGDA 15th international symposium onField Programmable Gate Arrays, 2007©EDA Publishing/THERMINIC 2008 151ISBN: 978-2-35500-008-9