Online proceedings - EDA Publishing Association

More documents

Recommendations

Info

[9] Coppersmith, D., Winograd S.: Matrix multiplication via arithmeticprogressions, J. Symbolic Computation 9, p. 251-280, 1990[10] Cyril Kowaliski: AMD's 2007 analyst day: Platforms and the glasshalf full http://techreport.com/articles.x/13792/2, on 21 August 2008.[11] Larry Seiler et al.: Larrabee: A Many-Core x86, Architecture for VisualComputing, ACM Transactions on Graphics, Vol. 27, No. 3, Article18, Publication date: August 2008KEYWORDSSUNRED, multithreading, Strassen, FDM, field simulation24-26 September 2008, Rome, ItalyBIOGRAPHYLászló Pohl is working as research assistant, post PhDstudent at Department of Electron Devices, Budapest Universityof Technology and Economics. He teaches programmingin C and C++ for students of informatics, electronicengineering and engineer-physicists. Research areas: applicationof the Finite Differences Method; simulation; thermaland electro-thermal investigations; OLEDs; computer architectures.©EDA Publishing/THERMINIC 2008 141ISBN: 978-2-35500-008-9
24-26 September 2008, Rome, ItalyThe Semiconductor - Dielectric Interface from PNJunction Periphery and its Influence on Reliabilityof Power Devices at High TemperatureV.V.N. ObrejaNational R&D Institute for Microtechnology (IMT – Bucuresti)Str. Erou Iancu Nicolae 126A, 077190, Bucharest, RomaniaAbstract - Data sheets of commercial power semiconductor devicesand modules available at this time on the market indicate amaximum permissible junction temperature specified in a rangeof 125 -200 o C. Operation above the specified value is not possiblewithout risk of device failure, although this is desirable inemerging power electronics applications. Typical device blockingelectrical characteristics at high junction temperature arepresented and analyzed. A portion of blocking current-voltagecharacteristic given by a PN junction at reverse bias voltage canbe fitted to linear variation. At higher applied voltage towards thebreakdown region deviation from linear variation is exhibited. Byincreasing the junction temperature from 150 o C towards 200 o Cand above this value, the portion of the current-voltagecharacteristic exhibiting linear variation becomes more reduced.If the applied voltage reaches the portion of electricalcharacteristic with deviation from linear variation towards thebreakdown region, thermal instability of the characteristic isdeveloped in short time. Device failure is possible if the appliedvoltage is not suppressed. Analysis of failed devices operated insuch conditions indicates excessive high current or even electricalshort-circuit for PN junctions at reverse applied voltage. It isshown that such behavior is due to a spot of material degradationlocated at the junction periphery. Most of leakage current flow ina thin interfacial layer between the semiconductor material andthe passivating dielectric material from the junction edge accountsfor many device failures during operation at high temperature.I. INTRODUCTIONDiscrete power semiconductor devices like diodes,transistors, thyristors or integrated modules have PN junctionscoated at their periphery with a dielectric material layer, [1-3].The interface between the semiconductor and dielectricmaterial from the junction periphery can have significantinfluence on the device current blocking capability.Nonetheless, this influence is usually neglected in theory andpractice. A high level of the leakage reverse current (I R ) ofsilicon PN junctions at high temperature is attributed tophenomena in the junction bulk, [4 - 5] and not to thephenomena from the interface. Due to high level of I R , themaximum operation junction temperature (T jmax ) of silicondevices is limited to 150 – 200 o C. Reliable operation at highertemperature value is desirable in applications. Above thespecified value of T jmax in the device data sheet, operation is atfailure risk because of local overheating at the junctionperiphery and instability of I R , [6-10]. Many failed devicesafter operation at high temperature exhibit loss of currentblocking capability due to electrical short-circuit of a PNjunction.The purpose of this work is to provide new results regardingthe influence of the silicon-dielectric interface from thejunction edge on reliability of high voltage silicon devicesduring operation at high temperature.II. DEVICE PN JUNCTION TERMINATIONS AND THESEMICONDUCTOR –DIELECTRIC INTERFACEPlanar and plane junction terminations are used in most ofcommercial power semiconductor devices available at thistime. Planar junctions under bias voltage are shown in Fig.1a,b.A silicon dioxide (SiO 2 ) layer covering the PN junctionperipheral region is usually used as passivating dielectricmaterial. For high voltage devices, outside the PN junction, P +diffused rings are used to improve the current blockingcapability. Direct transition from the semiconductor materialwith its properties to dielectric material with its properties, i.e.ideal interface like in Fig.1a is not possible. From the physicsof semiconductor surfaces it is known that a layer existingunder the terminating atoms has different properties incomparison with the bulk of semiconductor material. At thetransition between the semiconductor material and thedielectric material, a thin heterogeneous (or interfacial) layerformed by the terminating layer from semiconductor materialand the terminating layer from dielectric material is manifested.Such interfacial layer can include traces of foreign atoms ordefects remained at the semiconductor surface from cleaning orpossible contamination. At reverse bias voltage a depletionlayer is formed in the junction bulk (region delineated by thedotted line). In the case of ideal interface for planar junction(Fig.1a) or plane junction (Fig. 1c) the leakage reverse current,I R, is given only by current flow in the depletion layer. At thejunction periphery, this current blocking depletion layer is indirect contact with the dielectric layer and no current leakage ispossible at the interface. This is the model used in the theory ofjunction electrical characteristic. In this case, I R = I RB, where I RBis the leakage current caused by the bulk depletion layer.For real interface (Fig.1b and d) an extension of thedepletion layer in the thin interfacial layer with the same©EDA Publishing/THERMINIC 2008 142ISBN: 978-2-35500-008-9
Page 1 and 2:
http://cmp.imag.fr/conferences/ther
Page 3 and 4:
24-26 September 2008, Rome, Italy©
Page 5 and 6:
Page 7 and 8:
Page 9 and 10:
24-26 September 2008, Rome, ItalyBL
Page 11 and 12:
24-26 September 2008, Rome, ItalySe
Page 13 and 14:
24-26 September 2008, Rome, ItalyED
Page 15 and 16:
Staggered Cartesian meshes tolerate
Page 17 and 18:
VIII. THE CASE FOR MCAD-EMBEDDED EC
Page 19 and 20:
24-26 September 2008, Rome, ItalyTr
Page 21 and 22:
solution to the eikonal equation(
Page 23 and 24:
24-26 September 2008, Rome, ItalyS
Page 25 and 26:
24-26 September 2008, Rome, ItalyTr
Page 27 and 28:
24-26 September 2008, Rome, Italyda
Page 29 and 30:
q (RthΣ, t)q (R th , t )10.80.60.4
Page 31 and 32:
24-26 September 2008, Rome, ItalyEv
Page 33 and 34:
24-26 September 2008, Rome, Italy*R
Page 35 and 36:
24-26 September 2008, Rome, Italy[7
Page 37 and 38:
24-26 September 2008, Rome, ItalyNe
Page 39 and 40:
24-26 September 2008, Rome, ItalyS=
Page 41 and 42:
24-26 September 2008, Rome, ItalyVI
Page 43 and 44:
24-26 September 2008, Rome, Italyth
Page 45 and 46:
24-26 September 2008, Rome, Italypr
Page 47 and 48:
24-26 September 2008, Rome, ItalyFi
Page 49 and 50:
24-26 September 2008, Rome, ItalyPo
Page 51 and 52:
24-26 September 2008, Rome, ItalyWL
Page 53 and 54:
24-26 September 2008, Rome, ItalyTa
Page 55 and 56:
24-26 September 2008, Rome, ItalyII
Page 57 and 58:
Thermal resistance (K/W)0.250.200.1
Page 59 and 60:
24-26 September 2008, Rome, ItalyB.
Page 61 and 62:
temperatrue rise [K]76543210Sim0,00
Page 63 and 64:
24-26 September 2008, Rome, ItalyCo
Page 65 and 66:
24-26 September 2008, Rome, ItalyPr
Page 67 and 68:
Page 69 and 70:
24-26 September 2008, Rome, ItalyBl
Page 71 and 72:
conclusion, every tile is contacted
Page 73 and 74:
and B10), three space blocks (W4, W
Page 75 and 76:
24-26 September 2008, Rome, ItalyMu
Page 77 and 78:
After having determined the k eff v
Page 79 and 80:
24-26 September 2008, Rome, ItalyVI
Page 81 and 82:
24-26 September 2008, Rome, ItalyTh
Page 83 and 84:
PTjunc24-26 September 2008, Rome, I
Page 85 and 86:
tures - has been shown previously [
Page 87 and 88:
24-26 September 2008, Rome, ItalyAu
Page 89 and 90:
IV.CONCLUSIONSMentor Graphics Exped
Page 91 and 92:
24-26 September 2008, Rome, ItalyIn
Page 93 and 94:
III. HEDORIS SIMULATIONSThermal sim
Page 95 and 96:
24-26 September 2008, Rome, Italytr
Page 97 and 98:
24-26 September 2008, Rome, ItalyDe
Page 99 and 100:
24-26 September 2008, Rome, ItalyII
Page 101 and 102: datasheets, these values are usuall
Page 103 and 104: 24-26 September 2008, Rome, Italyte
Page 105 and 106: 24-26 September 2008, Rome, ItalyCo
Page 107 and 108: 24-26 September 2008, Rome, Italy20
Page 109 and 110: material to handle difficulties suc
Page 111 and 112: 24-26 September 2008, Rome, ItalyAt
Page 113 and 114: 24-26 September 2008, Rome, Italymo
Page 115 and 116: heatspreaders deposited during the
Page 117 and 118: 24-26 September 2008, Rome, ItalyTh
Page 119 and 120: 24-26 September 2008, Rome, Italyla
Page 121 and 122: Fig. 13 Transient of the output dio
Page 123 and 124: 24-26 September 2008, Rome, ItalyIn
Page 125 and 126: chamber to calibrate the thermal te
Page 127 and 128: V.Table 2: FE-Simulation test-matri
Page 131 and 132: 24-26 September 2008, Rome, Italy(c
Page 133 and 134: Case coverSupercapacitor n°2Electr
Page 135 and 136: 24-26 September 2008, Rome, Italyfr
Page 137 and 138: 24-26 September 2008, Rome, ItalyTA
Page 141 and 142: 24-26 September 2008, Rome, Italych
Page 143 and 144: 24-26 September 2008, Rome, ItalyDe
Page 145 and 146: Peltier control units (PCUs). The t
Page 149 and 150: every step: the fewer cells the mor
Page 151: TABLE IIEffect of multiplication-bl
Page 155 and 156: 24-26 September 2008, Rome, ItalyRe
Page 157 and 158: Drain source leakage current (A)Rev
Page 159 and 160: 24-26 September 2008, Rome, ItalyFP
Page 161 and 162: V IN =V DD /2Fig. 5. Short circuit
Page 165 and 166: The overall objective of the NANOPA
Page 167 and 168: 24-26 September 2008, Rome, ItalyRe
Page 169 and 170: predictions show that carbon nanotu
Page 171 and 172: 24-26 September 2008, Rome, ItalyFl
Page 173 and 174: 55. Campbell, R.C., S.E. Smith, and
Page 179 and 180: 24-26 September 2008, Rome, ItalyEX
Page 181 and 182: 24-26 September 2008, Rome, Italyen
Page 183 and 184: 24-26 September 2008, Rome, ItalyKE
Page 185 and 186: An original three-step etch process
Page 187 and 188: with a network of built-in sensors
Page 189 and 190: 24-26 September 2008, Rome, Italyan
Page 191 and 192: 24-26 September 2008, Rome, ItalyFu
Page 193 and 194: 24-26 September 2008, Rome, ItalyFi
Page 195 and 196: 24-26 September 2008, Rome, ItalyFi
Page 197 and 198: 24-26 September 2008, Rome, ItalyWe
Page 199 and 200: semiconductors is of the order of 1
Page 201 and 202: 24-26 September 2008, Rome, ItalyDu
Page 203 and 204:
transistor, through the bulk and be
Page 205 and 206:
impedance behaviour and on the othe
Page 207 and 208:
Tungstenmicro-heaterGas SensingMate
Page 209 and 210:
Tungsten micro-heater resistance (
Page 211 and 212:
24-26 September 2008, Rome, ItalyPo
Page 213 and 214:
24-26 September 2008, Rome, ItalyT3
Page 215 and 216:
24-26 September 2008, Rome, ItalyEv
Page 217 and 218:
24-26 September 2008, Rome, ItalyD.
Page 219 and 220:
24-26 September 2008, Rome, ItalyOn
Page 221 and 222:
24-26 September 2008, Rome, ItalyAc
Page 223 and 224:
24-26 September 2008, Rome, Italy
Page 225 and 226:
24-26 September 2008, Rome, ItalyLO
Page 227 and 228:
24-26 September 2008, Rome, Italymu
Page 229 and 230:
24-26 September 2008, Rome, Italy(R
Page 231 and 232:
Page 233 and 234:
24-26 September 2008, Rome, ItalyPa
Page 235 and 236:
24-26 September 2008, Rome, ItalyEl
Page 237 and 238:
Temperature rise (°C)1,81,61,41,21
Page 239 and 240:
i résistances carbone (A)i résist
Page 241 and 242:
calculates the dissipation distribu
Page 243 and 244:
in the next. It can also be used to
Page 245 and 246:
allows creating special methods of
Page 247 and 248:
OLED device (see Fig. 2.) provided
Page 249 and 250:
24-26 September 2008, Rome, ItalyFi
Page 251 and 252:
24-26 September 2008, Rome, ItalyIn
Page 253:
24-26 September 2008, Rome, ItalyWa
show all

Online proceedings - EDA Publishing Association

Create successful ePaper yourself

Delete template?

Save as template?