Lecture Notes in Computer Science 4917

Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm 95
Large reductions have been accomplished by:
– Optimization and simplification of the algorithm,
– Adding custom operations,
– Removing unused register files, issue slots and functional units,
– Introducing a loopcache,
– Introducing top-level clock gating,
– Introducing power gating of elements in SIMD operations.
The algorithmic optimization and simplification combined with custom operations resulted
in a reduced cycle count with a factor between 2 and 11, also the number of
words was reduced from 180 to 110 instruction words. Custom operations resulted in a
speed-up of a factor 5.
Customizing the architecture of the processor resulted in a reduced instruction word
size from 224 to 91 bit.
Top-level clock gating reduced the Idlepower consumption with a maximum of 1.2
mW. A loopcache reduced the power consumption to fetch an instruction word with a
factor 4.
When the processor is combined with features such as adaptive voltage control, leakage
power reduction and is tuned further to the application we believe that the energy
dissipation for each net data bit, compared to the ASIC, can be reduced with a maximum
of 70%.
Acknowledgement
This work is part of an innovation project at the High Tech Campus Eindhoven where
Silicon Hive and the Holst Centre cooperate. This paper is written in partial fulfillment
of obtaining a master’s degree in Electrical Engineering at the Eindhoven University of
Technology.
Thanks go out to M. Berekovic from IMEC-NL, J. Huisken from Silicon Hive, J.
van Meerbergen from Philips Research and O. Rousseaux from IMEC-NL for their
guidance and feedback.
References
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