Lecture Notes in Computer Science 4917

More documents

Recommendations

Info

276 A. García et al. whenever LPA captures a loop, the instructions belonging to each iteration of the loop are fetched from the loop window already decoded and renamed, avoiding the need for using the prediction, fetch, decoding, and renaming logic during almost all the loop execution. Our current LPA implementation only supports simple loop structures having a single control path inside. The appearance of an alternative path will be detected when a branch inside the loop body causes a misprediction. Therefore, the loop window is flushed at branch mispredictions, regardless the loop is still being stored or it is already being fetched from the loop window. After flushing the loop window contents, execution starts again using the normal prediction, fetch, decoding, and renaming logic. 2.1 The Renaming Mechanism The objective of the renaming logic is to remove data dependences between instructions by providing multiple storage locations (physical registers) for the same logical register. The target register of each renamed instruction receives a physical register that is used both to keep track of data dependences and to store the value produced by the instruction. The association between logical and physical registers is kept in a structure called rename table. Our loop window proposal is orthogonal to any prediction, fetch, and decode scheme, but it requires to decouple register renaming from physical register allocation. Instead of assigning a physical register to every renamed instruction, our architecture assigns a tag as done by virtual register [6]. This association is kept in a table that we call LVM (Logical-to-Virtual Map table). In this way, dependence tracking is effectively decoupled from value storage. Virtual tags are enough to keep track of data dependences, and thus physical register assignment is delayed until instructions are issued for execution, optimizing the usage of the available physical registers. The LVM is a direct mapped table indexed by the logical register number, that is, it has as many entries as logical registers exist in the processor ISA. Each entry contains the virtual tag associated to the corresponding logical register. When an instruction is renamed, the LVM is looked up to obtain the virtual tags associated to the logical source registers (a maximum of two read accesses per instruction). In addition, the target register receives a virtual tag from a list of free tags. The LVM is updated with the new association between the target register and the virtual tag to allow subsequent instructions getting the correct mapping (a maximum of one update access per instruction). Our virtual tags are actually divided into two subtags: the root virtual tag (rVT) and the iteration-dependent virtual tag (iVT). When a virtual tag is assigned to a logical register, the rVT field in the corresponding entry of the LVM receives the appropriate value from the list of free virtual tags, while the iVT field is initialized to zero. The instructions that do not belong to a captured loop will keep iVT to zero during all their execution, using just rVT for tracking dependences.
@00: add r4,r0,400 @04: add r5,r0,0 @08: add r1,0,4 @12: load r2,0(r4) @16: load r3,0(r4) @20: add r2,r3,r2 @24: add r5,r5,r2 @28: sub r4,r4,r1 @32: bneqz r4,@12 LPA: A First Approach to the Loop Processor Architecture 277 Loop Example LVM Updates LVM (after 1st iteration) virtual v1.0 assigned to logical r4 virtual v2.0 assigned to logical r5 virtual v3.0 assigned to logical r1 virtual v4.0 assigned to logical r2 virtual v5.0 assigned to logical r3 virtual v6.0 assigned to logical r2 (v4.0 out) virtual v7.0 assigned to logical r5 (v2.0 out) virtual v8.0 assigned to logical r4 (v1.0 out) Loop detected!! Loop branch is @32 First instruction is @12 Capturing Loop state starts Log rVT iVT I r1 v3 0 0 r2 v6 0 0 r3 v5 0 0 r4 v8 0 0 r5 v7 0 0 Fig. 3. Loop detection after the execution of its first iteration The transparency of this process is an important advantage of LPA: there is no need for functional changes in the processor design beyond introducing the loop window and the two-component virtual tag renaming scheme. The out-of-order superscalar execution core will behave in the same way regardless it receives instructions from the normal pipeline or from the loop window. 2.2 Loop Detection and Storage When a backward branch is predicted taken, LPA enters in the Capturing Loop state. Figure 3 shows an example of a loop structure that is detected by LPA at the end of its first iteration, that is, when the branch instruction finalizing the loop body is predicted taken. The backward branch is considered the loop branch and its target address is considered the first instruction of the loop body. Therefore, the loop body starts at instruction @12 and finalizes at the loop branch @32. During the Capturing Loop state, the instructions belonging to the loop body are stored in the loop window. Data dependences between these instructions are resolved using the renaming mechanism. Figure 3 shows a snapshot of the LVM contents after the first loop iteration. We assume that there are just five logical registers in order to simplify the graph. Instructions are renamed in program order. Each instruction receives a virtual tag that is stored in the corresponding rVT field, while the iVT field is initialized to zero. In addition, each LVM entry contains a bit (I) that indicates whether a logical register is inside a loop body and is iteration dependent. The I bit is always initialized to zero. The value of the I bit is only set to one for those logical registers that receive a new virtual register during the Capturing Loop state. An I bit set to one indicates that the associated logical register is iteration-dependent, that is, it is defined inside the loop body and thus its value is produced by an instruction from the current or the previous iteration.
Page 1 and 2:
Lecture Notes in Computer Science 4
Page 3 and 4:
Volume Editors Per Stenström Chalm
Page 5 and 6:
VI Preface The planning of a confer
Page 7 and 8:
VIII Organization Mahmut Kandemir P
Page 9 and 10:
Invited Program Table of Contents S
Page 11:
Table of Contents XIII Turbo-ROB: A
Page 14 and 15:
4 M. Valero and J. Labarta future s
Page 17 and 18:
MIPS MT: A Multithreaded RISC Archi
Page 19 and 20:
2.2 VPEs as Scheduling Domains MIPS
Page 21 and 22:
MIPS MT: A Multithreaded RISC Archi
Page 23 and 24:
6.1 Thread Context Virtualization M
Page 25 and 26:
8 Experimental Results MIPS MT: A M
Page 27 and 28:
Cycles/ Iteration MIPS MT: A Multit
Page 29:
9 Conclusions MIPS MT: A Multithrea
Page 32 and 33:
MPI: Message Passing on Multicore P
Page 34 and 35:
Page 36 and 37:
Page 38 and 39:
overhead per word (cycles) 1200 100
Page 40 and 41:
speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
Page 42 and 43:
speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
Page 44 and 45:
Page 46 and 47:
Page 48 and 49:
Modeling Multigrain Parallelism on
Page 50 and 51:
Page 52 and 53:
Page 54 and 55:
Page 56 and 57:
Page 58 and 59:
Page 60 and 61:
Page 63 and 64:
BRAM-LUT Tradeoff on a Polymorphic
Page 65 and 66:
32 L0 L1 BRAM-LUT Tradeoff on a Pol
Page 67 and 68:
Page 69 and 70:
Page 71 and 72:
Page 73:
Page 76 and 77:
Architecture Enhancements for the A
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
Page 88 and 89:
Page 90 and 91:
Page 92 and 93:
Implementation of an UWB Impulse-Ra
Page 94 and 95:
Page 96 and 97:
Page 98 and 99:
Page 100 and 101:
Page 102 and 103:
Page 104 and 105:
Page 107 and 108:
Fast Bounds Checking Using Debug Re
Page 109 and 110:
Page 111 and 112:
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121:
Page 124 and 125:
Studying Compiler Optimizations on
Page 126 and 127:
Page 128 and 129:
Page 130 and 131:
avg normalized execution time 1.000
Page 132 and 133:
Page 134 and 135:
Page 136 and 137:
Page 138 and 139:
Page 140 and 141:
CLI as an Effective Deployment Form
Page 142 and 143:
Page 144 and 145:
Page 146 and 147:
Page 148 and 149:
Page 150 and 151:
Page 152 and 153:
Page 155 and 156:
Compilation Strategies for Reducing
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
180% 160% 140% 120% 100% 80% 60% 40
Page 169 and 170:
Experiences with Parallelizing a Bi
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Page 179 and 180:
Page 181 and 182:
Page 183:
Page 186 and 187:
Drug Design Issues on the Cell BE 1
Page 188 and 189:
Page 190 and 191:
Page 192 and 193:
Page 194 and 195:
speed-up 8 6 4 2 0 FFT3D 256 64-A F
Page 196 and 197:
Page 198 and 199:
Page 201 and 202:
COFFEE: COmpiler Framework for Ener
Page 203 and 204:
Page 205 and 206:
Benchmark Source Code * transformed
Page 207 and 208:
Page 209 and 210:
RTL for each Component * Gate−lev
Page 211 and 212:
Page 213 and 214:
Normalized Cycle Count 1.00 0.90 0.
Page 215 and 216:
Page 217 and 218:
Integrated CPU Cache Power Manageme
Page 219 and 220:
Page 221 and 222:
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231:
Page 234 and 235: Variation-Aware Software Techniques
Page 244 and 245: Average leakage-power saving (%) Va
Page 250 and 251: 244 Y. Sazeides et al. of mispredic
Page 252 and 253: 246 Y. Sazeides et al. Affector BB1
Page 254 and 255: 248 Y. Sazeides et al. 2.3 How to U
Page 256 and 257: 250 Y. Sazeides et al. Cumulative D
Page 258 and 259: 252 Y. Sazeides et al. ijpeg, andbo
Page 260 and 261: 254 Y. Sazeides et al. Misses/KI 12
Page 262 and 263: 256 Y. Sazeides et al. Mahlke and N
Page 265 and 266: Turbo-ROB: A Low Cost Checkpoint/Re
Page 267 and 268: 260 P. Akl and A. Moshovos Original
Page 269 and 270: 262 P. Akl and A. Moshovos Oldest I
Page 271 and 272: 264 P. Akl and A. Moshovos new firs
Page 273 and 274: 266 P. Akl and A. Moshovos throttli
Page 275 and 276: 268 P. Akl and A. Moshovos 80% 70%
Page 277 and 278: 270 P. Akl and A. Moshovos 25% 20%
Page 279: 272 P. Akl and A. Moshovos [4] Burg
Page 282 and 283: 274 A. García et al. execution tim
Page 286 and 287: 278 A. García et al. @12: load r2,
Page 288 and 289: 280 A. García et al. Target Loop E
Page 290 and 291: 282 A. García et al. reduction 100
Page 292 and 293: 284 A. García et al. IPC speedup 7
Page 294 and 295: 286 A. García et al. SPECfp benchm
Page 297 and 298: Complementing Missing and Inaccurat
Page 299 and 300: 90 100 100 25 75 25 25 100 100 10 1
Page 307 and 308: 6.1 Filling Edge Profile from Verte
Page 311 and 312: Using Dynamic Binary Instrumentatio
Page 313 and 314: L1 D-Cache Miss Rate (%) CPI 5 4 3
Page 319 and 320: CPI Error (%) 10 5 0 -5 -10 FP Resu
Page 321 and 322: CPI Error (%) 40 30 20 10 0 Using D
Page 325: Using Dynamic Binary Instrumentatio
Page 328 and 329: Phase Complexity Surfaces: Characte
Page 334 and 335:
Phase Complexity Surfaces: Characte
Page 336 and 337:
( log10) phases of Number 4.0 3.5 3
Page 338 and 339:
Page 340 and 341:
Page 343 and 344:
MLP-Aware Dynamic Cache Partitionin
Page 345 and 346:
Page 347 and 348:
Page 349 and 350:
Page 351 and 352:
Page 353 and 354:
(a) IPC as we vary the number of as
Page 355 and 356:
Page 357 and 358:
Page 359 and 360:
Compiler Techniques for Reducing Da
Page 361 and 362:
Page 363 and 364:
Page 365 and 366:
Page 367 and 368:
Page 369 and 370:
Page 371 and 372:
40 35 30 25 ) te ( % 20 -ra M is s
Page 373 and 374:
References Compiler Techniques for
Page 375 and 376:
Code Arrangement of Embedded Java V
Page 377 and 378:
Page 379 and 380:
Page 381 and 382:
Page 383 and 384:
Page 385 and 386:
Page 387 and 388:
Page 389:
Page 392 and 393:
Aggressive Function Inlining: Preve
Page 394 and 395:
f1(){ ...g();....} f2(){....q();...
Page 396 and 397:
Page 398 and 399:
Page 400 and 401:
foo:(80 times) BB1: Call bar BB2: C
Page 402 and 403:
Page 404 and 405:
Page 406:
400 Author Index Shajrawi, Yousef 3
show all

Lecture Notes in Computer Science 4917

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?