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Lecture Notes in Computer Science 4917

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36 J. Psota and A. Agarwal<br />

rMPI was designed to leverage the unique architectural resources that a multicore processor<br />

architecture with on-chip networks and direct access to hardware resources such<br />

as Raw provides.<br />

A number of evaluations us<strong>in</strong>g the rMPI implementation show that its overhead,<br />

especially for applications with many short messages on multicores such as Raw, illustrates<br />

that MPI is likely not the optimal <strong>in</strong>terface for multicores with on-chip <strong>in</strong>terconnect,<br />

as it imposes significant overhead on all communication. Furthermore, rMPI’s<br />

large memory footpr<strong>in</strong>t makes it less well-suited for multicore’s generally smaller onchip<br />

<strong>in</strong>struction caches. Overall, this work shows that MPI is too heavyweight for multicores<br />

with on-chip networks such as Raw, and suggests that a lighter-weight multicore<br />

programm<strong>in</strong>g <strong>in</strong>terface that takes advantage of low latency networks and has a smaller<br />

memory footpr<strong>in</strong>t be developed. The authors hope that this work provides guidance<br />

and useful <strong>in</strong>sights to application developers of future multicore processors conta<strong>in</strong><strong>in</strong>g<br />

on-chip <strong>in</strong>terconnect.<br />

References<br />

1. Intel pentium d,<br />

http://www.<strong>in</strong>tel.com/products/processor/pentium d/<br />

2. Moore’s law 40th anniversary,<br />

http://www.<strong>in</strong>tel.com/technology/mooreslaw/<strong>in</strong>dex.htm<br />

3. The multicore association communications api,<br />

http://www.multicore-association.org/workgroup/ComAPI.html<br />

4. Transputer reference manual. Prentice Hall International (UK) Ltd. Hertfordshire, UK (1998)<br />

5. Borkar, S., Cohn, R., Cox, G., Gleason, S., Gross, T., Kung, H.T., Lam, M., Moore, B.,<br />

Peterson, C., et al.: iwarp: An <strong>in</strong>tegrated solution to high-speed parallel comput<strong>in</strong>g. In: Proceed<strong>in</strong>gs<br />

of Supercomput<strong>in</strong>g (1998)<br />

6. Burns, G., Daoud, R., Vaigl, J.: LAM: An Open Cluster Environment for MPI. In: Proceed<strong>in</strong>gs<br />

of Supercomput<strong>in</strong>g Symposium, pp. 379–386 (1994)<br />

7. Espasa, et al.: Tarantula: A Vector Extension to the Alpha Architecture. In: ISCA, pp. 281–<br />

292 (2002)<br />

8. T.J., et al.: POWER4 system microarchitecture. IBM Journal of Research and Development<br />

46(1), 5–25 (2002)<br />

9. Forum, M.: A message pass<strong>in</strong>g <strong>in</strong>terface standard. Technical report, University of Tennessee,<br />

Knoxville (1994)<br />

10. Forum, M.P.I.: Mpi: A message-pass<strong>in</strong>g <strong>in</strong>terface standard (1995),<br />

http://www.mpi-forum.org/docs/mpi-11-html/mpi-report.html<br />

11. Gabriel, E., Fagg, G.E., Bosilca, G., Angskun, T., Dongarra, J.J., Squyres, J.M., Sahay,<br />

V., Kambadur, P., Barrett, B., Lumsda<strong>in</strong>e, A., Casta<strong>in</strong>, R.H., Daniel, D.J., Graham, R.L.,<br />

Woodall, T.S.: Open MPI: Goals, concept, and design of a next generation MPI implementation.<br />

In: Proceed<strong>in</strong>gs, 11th European PVM/MPI Users’ Group Meet<strong>in</strong>g, Budapest, Hungary,<br />

pp. 97–104 (September 2004)<br />

12. Gordon, M.I., Thies, W., Karczmarek, M., L<strong>in</strong>, J., Meli, A.S., Lamb, A.A., Leger, C., Wong,<br />

J., Hoffmann, H., Maze, D., Amaras<strong>in</strong>ghe, S.: A Stream Compiler for Communication-<br />

Exposed Architectures. In: Conference on Architectural Support for Programm<strong>in</strong>g Languages<br />

and Operat<strong>in</strong>g Systems, pp. 291–303 (2002)<br />

13. Griff<strong>in</strong>, P.: CFlow. Master’s thesis, Lab for <strong>Computer</strong> <strong>Science</strong>, MIT (2005)

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