Lecture Notes in Computer Science 4917

IPC speedup
30%
25%
20%
15%
10%
5%
0%
164.gzip
175.vpr
176.gcc
181.mcf
LPA: A First Approach to the Loop Processor Architecture 283
4-wide front-end with 6-wide LW
6-wide front-end without LW
186.crafty
197.parser
252.eon
(a) SPECint
253.perlbmk
254.gap
255.vortex
256.bzip2
300.twolf
AVG
IPC speedup
30%
25%
20%
15%
10%
5%
0%
168.wupwise
171.swim
4-wide front-end with 6-wide LW
6-wide front-end without LW
172.mgrid
173.applu
177.mesa
178.galgel
179.art
183.equake
187.facerec
(b) SPECfp
188.ammp
189.lucas
191.fma3d
200.sixtrack
301.apsi
AVG
Fig. 8. Performance speedup over a 4-wide front-end processor (back-end is always
6-wide)
achieve 4.5% speedup. The improvement is larger for SPECfp benchmarks because
branch instructions are better predicted, and thus it is possible to extract
more ILP.
The left bar shows the speedup achieved when the front-end is still limited to
4 instructions, but a loop window able to fetch up to 6 instructions per cycle is
included. This loop window allows reducing the front-end activity. In addition,
a 4-instruction wide front-end is less complex than a 6-wide one. However, it
becomes clear from these results that adding a loop window is not enough for
the 4-wide front-end to achieve the performance of the 6-wide front-end. It only
achieves comparable performance in a few benchmarks like 176.gcc, 200.sixtrack,
and 301.apsi. On average, SPECint benchmarks achieve 1% IPC speedup and
SPECfp achieve 2.3% speedup.
The loop window is not able to reach the performance of a wider processor
front-end because the most important back-end structures are completely full
most of the time, that is, back-end saturation is limiting the potential benefit of
our proposal. Figure 9 shows performance speedup for the same setups previously
shown in Figure 8, but using an unbounded back-end, that is, the ROB, the issue
queues, and the register file are scaled to infinite.
The loop window achieves higher performance speedups for SPECint and
especially SPECfp benchmarks. Furthermore, the loop window using a 4-wide
front-end achieves better performance than the 6-wide front-end in several benchmarks:
176.gcc (SPECint), 172.mgrid, 178 galgel, and 179.art. Those benchmarks
have a high amount of simple dynamic loops, enabling the loop window
to fetch instructions at a faster rate than normal front-end most of time.
5 Related Work
To exploit instruction level parallelism, it is essential to have a large window
of candidate instructions available to issue. Reusing loop instructions is a wellknown
technique in this field, since the temporal locality present in loops provides
a good opportunity for loop caching. Loop buffers were developed in the sixties
for the CDC 6600/6700 series [9] to minimize the time wasted due to conditional