Lecture Notes in Computer Science 4917

COFFEE: COmpiler Framework for Energy-Aware Exploration 195
is accurate, but requires the hardware design to be completed, which restricts thorough
exploration. Energy estimation at ISA level, enables such a fast estimation, by trading
off some accuracy for speed. The energy estimation of the proposed framework has
been validated against a real design.
The novel contributions of this paper include the following:
1. an accurate ISA level and profiling level energy estimation, early in the design flow
2. a framework that enables simulation and compilation for a wide range of state of
the art processors and advanced low power architectural extensions
3. an integrated framework, which is automated to a large extent, to perform code
transformations, compilation, simulation and energy estimation
The rest of the paper is organized as follows. Section 2 gives an overview of frameworks
that support co-design exploration. Section 3 introduces the proposed framework,
describes the modeled components and the exploration space. Section 4 illustrates the
energy estimation process for different components of the processor and estimation of
the energy consumption of the complete platform. Section 5 describes the results and
analysis for representative optimizations in the embedded context for a WCDMA application
using the proposed flow. Finally Section 6 gives a summary and outlines the
future work.
2 Related Work
Various attempts to make retargetable compiler and architectural level exploration tools
have been made: e.g. Trimaran [1], Simplescalar [2] and Epic Explorer [3]. All these
frameworks are capable of exploring a restricted design space and do not support important
architectural features like software controlled memories, data parallelism or SIMD
(Single Instruction Multiple Data), clustered register files, loop buffers etc. These features
have become extremely important for embedded handheld devices as energy efficiency
is a crucial design criterion. Although these frameworks (except Epic Explorer)
do not directly provide energy estimation, several extensions have been built for this
purpose. Wattch [4] and SimplePower, for example, are based on Simplescalar, but
their power models are not geared towards newer technologies and their parameter
range is still too restricted. Other industrial tools like Target’s Chess/Checkers, Tensilica’s
XPRES and Coware’s Processor Designer provide architectural and compiler
retargetability, but the supported design space is limited to a restricted template and
they do not provide fast, high-level energy estimates. Detailed energy estimates can be
obtained by synthesizing the generated RTL and using the traditional hardware design
flow. Generating such detailed estimates are too time consuming for wide exploration
and for evaluating compiler and architectural optimizations. Energy estimates based on
a library of architectural components, as proposed in this paper, do not suffer from these
drawbacks, as they are fast and sufficiently accurate for these purposes.
In the code transformation space SUIF [5] pioneered enabling loop transformations
and analysis. Wrap-IT [6] from INRIA uses the polyhedral model for analysis and to
perform transformations. These tools alone are not sufficient as transformations can
have an impact (positive, negative or neutral) on various parts of the processors. This is