Lecture Notes in Computer Science 4917

188 H. Servat et al.
1.5GHz POWER5 chips with 16GBytes of RAM. Each POWER5 chip is dualcore
and dual-thread (giving a total of 8 threads on the system). The parallel
version of the FTDock for that multicore uses the FFTW3.2alpha2 library in
order to do the 3D FFT, and consists on dividing the rotations among different
tasks using OpenMPI. Therefore, we are comparing a coarse-grain parallelization
on that multicore against a fine-grain parallelization on a Cell BE.
Figure 8 shows the total execution times of FTDock for 1, 2, 4 and 8 tasks
or SPEs on a POWER5 multicore and on a Cell BE respectively, for 128 3 and
256 3 grid sizes. We can see that Cell BE FTDock outperforms that multicore
parallel implementation of the FTDock. The reasons seems to be the same that
we commented when comparing PPU and SPU on Section 6.2. Memory hierarchy
becomes a bottleneck for the POWER5 tasks, meanwhile SPEs of the Cell BE
avoid the MSHR limitation accessing to main memory. Moreover, Cell is more
cost-effective and more power-efficient than the POWER5 multicore [24].
seconds
400
300
200
100
0
CellBE
POWER5 multicore
1 2 4 8
SPEs
a) 128 3 grid size
seconds
3000
2000
1000
0
CellBE
POWER5 multicore
1 2 4 8
SPEs
b) 256 3 grid size
Fig. 8. Total execution time of the parallel implementation of FTDock for a multicore
POWER5 and a CellBE for 128 3 grid size(left), and 256 3 grid size (right)
8 Conclusions
In this paper we have evaluated and analyzed an implementation of a protein
docking application, FTDock, on a Cell BE Blade using different algorithm parameters
and levels of parallelization.
We have achieved a significant speedup of FTDock when we have offloaded
the most time consuming functions to the SPEs. However, improving the PPU
processor and its memory hierarchy would improve the potential of Cell BE for
applications that can not be completely offloaded to the SPEs. Indeed, increasing
the number of SPEs per task (one thread running on one PPE) improves the
performance of the application. However, linear speedup is not achieved because
main memory and EIB contention increases when several SPEs access to main
memory in the same Cell BE. Therefore, one should parallelize the application
in such a way the main memory and EIB contention is distributed between the
two Cell BE of the blade [18].
The relatively small Local Store of the SPE increases the main memory accesses
in order to keep partial results. With FTDock, we have seen that increasing