Lecture Notes in Computer Science 4917

COFFEE: COmpiler Framework for Energy-Aware Exploration 203
We have used the proposed compiler and simulator flow to optimize the WCDMA
receiver code from [23] for a baseline VLIW processor. Starting from the detailed performance
estimate on the complete code, the receiver filter (Rx Filter in Figure 5) was
identified to be the single most important part of the application in terms of computational
requirements and energy consumption (85% percent of the WCDMA’s Receiver
cycles). Optimizing code transformations using the URUK flow will be illustrated on
this part.
It should be emphasized here that the presented COFFEE framework can be used for
any ANSI-C compliant application. WCDMA is shown as a relevant example from our
target application domain, being multimedia and wireless communication algorithms
for portable devices.
5.2 Processor Architectures
The wide range of architectural parameters supported by the presented framework allows
designers to explore many different architectural styles and variants quickly. It
enables experiments with combinations of parameters or components not commonly
found in current processors. In the experimental results shown here, we have optimized
the WCDMA receiver filter for two architectures described in this subsection, as an
example of the range and complexity of architectures that can be supported.
TI C64-like VLIW processor. The TI C64 [10] is a clustered VLIW processor with
two clusters of 4 Functional Units (FUs) each. This processor is chosen as a typical
example of an Instruction Level Parallel (ILP) processor. In this heterogeneous VLIW
each FU can perform a subset of all supported operations. The Instruction Set Architecture
(ISA) and the sizes of memory hierarchy are modeled as described in [10]. The
TIC64 also supports a number of hardware accelerators (e.g. Viterbi decoder). These
blocks can be correctly modeled by our flow by using intrinsics, but since are not needed
for the WCDMA benchmark, they are not modeled in this case study.
ARM Cortex A8-like processor. The Cortex A8 processor [14] is an enhanced
ARMv7 architecture with support for SIMD, and is used here as a typical example
of a Data Level Parallel (DLP) architecture. The processor consists of separate scalar
and vector datapaths. Each datapath has a register file and specialized FUs. The vector
units in the vector datapath support up to 128-bit wide data in various subword modes.
The FUs have a different number of execute stages, which result in different latencies.
The details of the modeled architecture including its memory hierarchy can be found in
[14].
Novel Design Space architectures. To illustrate the wide design space that is supported
by our tools, we start with a standard processor and modify the most power
consuming parts of it. Both architectures are shown in shown in Figure 6. Architecture
A is a 4 issue homogeneous VLIW with a 4kB L1 data cache, 4kB L1 instruction memory
and a centralized register file of 32 deep, 12 ports. Architecture B optimizes some
important parts of the architecture: the cache is replaced with a data scratchpad memory
and a DMA, the L1 instruction memory is enhanced with a distributed loop buffer