Lecture Notes in Computer Science 4917

Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array 77
Table 5. Comparing base (100MHz) with final instance (312MHz)
Total MIPS MIPS/mW mW/MHz
Power Energy
(mW) (uJ)
FFT
Base 73.28 0.619 759 10.35 0.7328
Final 67.29 0.307 1190 17.68 0.2153
Improve
IDCT
8.17% 50.4% 56.78% 70.82% 70.62%
Base 80.45 37.72 1409 17.51 0.8045
Final 81.99 19.14 2318 28.27 0.2624
Improve -1.91% 49.25% 64.51% 61.45% 67.38%
5.1 Putting It All Together
Combining the arch 8 architecture with the aforementioned optimizations results in
a low power, high performance ADRES instance: 4x4 arch 8 4L final. A comparison
between the proposed architecture with the base architecture (shown in Figure 1) is
provided in Table 5. The results indicate a moderate improvement in power of 8%, but
with a higher performance of 56 - 65% due to the pipelining and routings features. This
results in lower energy dissipation of the architecture by 50%. The area of the proposed
architecture was improved from 1.59mm 2 (544k gates) to 1.08mm 2 (370k gates), which
is equivalent to a 32% improvement.
5.2 Final Architecture Power Decomposition
The final 4x4 arch 8 4L final architecture is placed and routed using Cadence SOC
Encounter v4.2. The power and area of the proposed architecture layout are decomposed
in Figures 12(a) and 12(b), respectively. These figures are of the ADRES core
architecture excluding data and instruction memories. Due to the fact that the final architecture
is pipelined the clock tree contribution (4.67mW) is included in these figures.
The data memory and the instruction cache were not included in the synthesis for which
no power estimations are made. The multiplexors in the CGA datapath were removed
during synthesis by the synthesis tool as this was beneficial for performance.
Comparing Figure 3 with Figure 12(a) we notice that the shared local DRFs combined
with clock gating results in lower power consumption. The configuration memories
still require a vast amount of power and area, but have decreased in size as well.
Further optimizations of the configuration memories require advance power management
e.g. power gating, which was not applied in the final architecture. Interesting to
note is the relatively higher power consumption of the CGA FUs compared to Figure 3.
This is caused by the higher utilization of the array compared to the base architecture
consuming more power, but providing higher performance. This increases power efficiency
as noticeable in Table 3. The 16 CGA FUs and the CMs require 68.66% of all
the area as depicted in Figure 12(b). The largest single component is the global DRF
(noted as drf vliw) with 8 read and 4 write ports.