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Lecture Notes in Computer Science 4917

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Code Arrangement of Embedded Java Virtual Mach<strong>in</strong>e for NAND Flash Memory 377<br />

bytecode handlers were located <strong>in</strong> dist<strong>in</strong>ct NAND flash pages, each bytecode<br />

<strong>in</strong>struction decod<strong>in</strong>g operation would cause a cache miss. This is because the next-toexecute<br />

bytecode handler is always located <strong>in</strong> an uncached NAND flash page. In the<br />

other word, the sample sequence caused at least eight cache misses. Nevertheless, if<br />

both the handlers of A and B are grouped to the same page, cache misses will decl<strong>in</strong>e<br />

to 5 times, and the page access trace becomes:<br />

fault-A-B-A-B-fault-C-fault-D-fault-E-fault-C<br />

If we expand the group (A, B) to <strong>in</strong>clude the handler of C, the cache miss count<br />

would even drop to four times, and the page access trace looks like the follow<strong>in</strong>g one:<br />

fault-A-B-A-B-C-fault-D-fault-E-fault-C<br />

Therefore, an effective code layout method should partition all bytecode<br />

<strong>in</strong>structions <strong>in</strong>to disjo<strong>in</strong>ed sets based on their execution relevance. Each NAND flash<br />

page conta<strong>in</strong>s one set of bytecode handlers. Partition<strong>in</strong>g the ICFG can reach this goal.<br />

Back to Figure 8, the directed edges represented the temporal order of the<br />

<strong>in</strong>struction sequence. The weight of an edge is the repetitious count that the bytecode<br />

<strong>in</strong>struction succeeded to the other <strong>in</strong> the <strong>in</strong>struction sequence. If we cut off edge (B,<br />

C), the ICFG is divided <strong>in</strong>to two disjo<strong>in</strong>ed sets. That is, the bytecode handlers of A<br />

and B are placed <strong>in</strong> one page, and the bytecode handlers of C, D, and E are placed <strong>in</strong><br />

the other. The page access trace became:<br />

fault-A-B-A-B-fault-C-D-E-C<br />

This placement would cause only two cache misses, which is 75% lower than the<br />

worst case! The next step is to transform the ICFG diagram to an undirected graph by<br />

merg<strong>in</strong>g opposite direction edges connected same vertices, and weight of the<br />

undirected edge is the sum of weights of those two directed edges. The consequence<br />

is actually a derivation of the classical MIN k-CUT problem. Formally speak<strong>in</strong>g,<br />

given a graph G(V, E), it can be modeled as:<br />

� Vi – represent the i-th bytecode <strong>in</strong>struction.<br />

� Ei,j – the edge connect i-th and j-th bytecode <strong>in</strong>struction.<br />

� Fi,j – number of times that two bytecode <strong>in</strong>structions i and j executed after each<br />

other. It is the weight of edge Ei,j.<br />

� K – number of expected partitions.<br />

� Wx,y – the <strong>in</strong>tra-set weight. x≠y, Wx,y= ΣFi,j where Vi ∈ Px and Vj ∈ Py.<br />

The goal is to model the problem as the follow<strong>in</strong>g def<strong>in</strong>ition:<br />

Def<strong>in</strong>ition 1. The MIN k-CUT problem is to divide G <strong>in</strong>to K disjo<strong>in</strong>ed partitions {P1,<br />

P2,…,Pk}. Such that ΣWi,j is m<strong>in</strong>imized.<br />

4.3 The Mathematical Model<br />

Yet there was another constra<strong>in</strong>t on our program. Gather<strong>in</strong>g bytecode <strong>in</strong>structions for<br />

partitions regardless of total size of handlers is impractical, s<strong>in</strong>ce the size of each<br />

bytecode handler is dist<strong>in</strong>ct, and the total code size of a partition cannot exceed the<br />

size of a NAND flash page. Our aim is to distribute bytecode handlers <strong>in</strong>to several<br />

disjo<strong>in</strong>ed partitions {P1, P2,…,Pk}. We def<strong>in</strong>ed the follow<strong>in</strong>g notations:

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