Lecture Notes in Computer Science 4917

6.1 Thread Context Virtualization
MIPS MT: A Multithreaded RISC Architecture 15
User-mode code has no knowledge of which physical TC it is using, nor which physical
TC is allocated by a successful FORK instruction. All interaction between concurrently
executing threads is done via shared memory or memory-like storage, and there is no
architectural assumption made about whether it is the “parent” or “child” which executes
first after a FORK.
When a FORK instruction is issued, it is transparent to the application whether a TC
was allocated and launched, or whether a thread overflow exception was taken instead.
In response to the thread overflow exception, an operating system has the option of
treating it as a fatal application error, treating it as an exception to be raised to the application,
or emulating the operation.
Emulation of a FORK implies hybrid scheduling, wherein the multithreaded processor
schedules among the threads resident in N TCs, while system software multiplexes
M>N software threads across those N TCs. The MIPS MT architecture facilitates this
with MFTR (Move From Thread Register) and MTTR (Move To Thread Register) instructions,
which allow a privileged thread running on one TC to halt another TC and
manipulate its contents, and with the per-TC scheduling feedback registers that allow
the forward progress of each thread to be monitored.
TCs which are blocked on ITC references or YIELD instructions may be halted and
swapped-out without any side-effect on the software-visible state of the thread or of the
ITC storage.
6.2 ITC Storage Virtualization
ITC storage is a special case of physical memory, and can be mapped and protected by
the MIPS32 MMU. Unlike physical memory, ITC storage cannot be swapped in or out
with direct I/O operations. System software must extract and restore both the cell data
and the cell control state, via the bypass and control views, respectively.
6.3 YIELD Qualifier Virtualization
The MIPS MT architecture exposes a new set of physical inputs, the YIELD qualifiers,
to user-mode software. To allow for trap and emulation of qualified YIELD
operations, each VPE has a privileged mask register to selectively enable the YIELD
qualifiers. If an application’s YIELD instruction attempts to wait on an input that has not
been enabled in the associated mask, an exception is taken. The operating system can
then implement an appropriate policy of termination, raising of a software exception, or
emulation of the YIELD with a software suspension of the thread.
7 Software Use Models
The flexibility of the MIPS MT architecture as a multithreading framework has been
demonstrated in the development of four different operating system models. All of them
proved usable, and each has its distinct advantages.