Lecture Notes in Computer Science 4917

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Per Stenström Michel Dubois Manolis Katevenis Rajiv Gupta Theo Ungerer (Eds.) High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008 Göteborg, Sweden, January 27-29, 2008 Proceedings 13
Volume Editors Per Stenström Chalmers University of Technology, Dept. of Computer Science and Engineering 412 96 Gothenburg, Sweden E-mail: pers@chalmers.se Michel Dubois University of Southern California, Dept. of Electrical Engineering 3740 McClintock Ave., Los Angeles, CA 90089-2562, USA E-mail: dubois@paris.usc.edu Manolis Katevenis FORTH-ICS 100 Plastira Ave., Vassilika Vouton, 70-013 Heraklion, Crete, Greece E-mail: kateveni@ics.forth.gr Rajiv Gupta University of California, Riverside, Dept. of Computer Science and Engineering 408 Engineering Building II, Riverside, CA 92521, USA E-mail: gupta@cs.ucr.edu Theo Ungerer University of Augsburg, Institute of Computer Science 86135 Augsburg, Germany E-mail: ungerer@informatik.uni-augsburg.de Library of Congress Control Number: 2007942570 CR Subject Classification (1998): B.2, C.1, D.3.4, B.5, C.2, D.4 LNCS Sublibrary: SL 1 – Theoretical Computer Science and General Issues ISSN 0302-9743 ISBN-10 3-540-77559-5 Springer Berlin Heidelberg New York ISBN-13 978-3-540-77559-1 Springer Berlin Heidelberg New York This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, re-use of illustrations, recitation, broadcasting, reproduction on microfilms or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer. Violations are liable to prosecution under the German Copyright Law. Springer is a part of Springer Science+Business Media springer.com © Springer-Verlag Berlin Heidelberg 2008 Printed in Germany Typesetting: Camera-ready by author, data conversion by Scientific Publishing Services, Chennai, India Printed on acid-free paper SPIN: 12212101 06/3180 5 4 3 2 1 0
Page 1: Lecture Notes in Computer Science 4
Page 5 and 6: VI Preface The planning of a confer
Page 7 and 8: VIII Organization Mahmut Kandemir P
Page 9 and 10: Invited Program Table of Contents S
Page 11: Table of Contents XIII Turbo-ROB: A
Page 14 and 15: 4 M. Valero and J. Labarta future s
Page 17 and 18: MIPS MT: A Multithreaded RISC Archi
Page 19 and 20: 2.2 VPEs as Scheduling Domains MIPS
Page 21 and 22: MIPS MT: A Multithreaded RISC Archi
Page 23 and 24: 6.1 Thread Context Virtualization M
Page 25 and 26: 8 Experimental Results MIPS MT: A M
Page 27 and 28: Cycles/ Iteration MIPS MT: A Multit
Page 29: 9 Conclusions MIPS MT: A Multithrea
Page 32 and 33: MPI: Message Passing on Multicore P
Page 38 and 39: overhead per word (cycles) 1200 100
Page 40 and 41: speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
Page 42 and 43: speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
Page 48 and 49: Modeling Multigrain Parallelism on
Page 50 and 51: Modeling Multigrain Parallelism on
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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Architecture Enhancements for the A
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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avg normalized execution time 1.000
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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180% 160% 140% 120% 100% 80% 60% 40
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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speed-up 8 6 4 2 0 FFT3D 256 64-A F
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Normalized Cycle Count 1.00 0.90 0.
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Integrated CPU Cache Power Manageme
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Variation-Aware Software Techniques
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Average leakage-power saving (%) Va
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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Turbo-ROB: A Low Cost Checkpoint/Re
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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266 P. Akl and A. Moshovos throttli
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268 P. Akl and A. Moshovos 80% 70%
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270 P. Akl and A. Moshovos 25% 20%
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272 P. Akl and A. Moshovos [4] Burg
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274 A. García et al. execution tim
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276 A. García et al. whenever LPA
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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Complementing Missing and Inaccurat
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90 100 100 25 75 25 25 100 100 10 1
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6.1 Filling Edge Profile from Verte
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Using Dynamic Binary Instrumentatio
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L1 D-Cache Miss Rate (%) CPI 5 4 3
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CPI Error (%) 10 5 0 -5 -10 FP Resu
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CPI Error (%) 40 30 20 10 0 Using D
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Phase Complexity Surfaces: Characte
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( log10) phases of Number 4.0 3.5 3
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MLP-Aware Dynamic Cache Partitionin
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(a) IPC as we vary the number of as
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Compiler Techniques for Reducing Da
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40 35 30 25 ) te ( % 20 -ra M is s
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References Compiler Techniques for
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Code Arrangement of Embedded Java V
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Aggressive Function Inlining: Preve
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f1(){ ...g();....} f2(){....q();...
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foo:(80 times) BB1: Call bar BB2: C
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400 Author Index Shajrawi, Yousef 3
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Lecture Notes in Computer Science 4917

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