Lecture Notes in Computer Science 4917

14 K.D. Kissell
of a thread. A processor implementing MIPS MT has up to 31 yield qualifier inputs, to
be connected to indicators of events external to the core. When a YIELD instruction is
issued with a positive input operand value, that value is interpreted as a vector of orthogonal
bits corresponding to the yield qualifier inputs. If none of the qualifier inputs
corresponding to the operand value are asserted, execution of the thread is suspended
until such time as one of them goes active.
The ability to suspend execution based on a particular yield qualifier can be controlled
by the operating system, using a privileged mask register. If a program issues a YIELD
where the input value has a set bit that is not set in the mask register, an exception is delivered
on the YIELD. This allows operating systems to prevent unauthorized programs
using input state as a covert channel, and allows virtualization, whereby a program executing
on a VPE to which a particular yield qualifier input is not connected can have the
YIELD operation emulated by the OS, in response to the illegal qualifier exception.
Event service gated by YIELD instructions has potentially less latency than interrupts,
even those handled by dedicated interrupt threads or shadow register files, because
in addition to eliminating the need to save and restore context, there is no control
transfer to a vector, which would typically require a pipeline flush, and no decode of
state to determine where to resume event processing. In the case of the 34K-family
cores, which have a per-TC instruction buffer (IB), the instruction following the YIELD
is generally already in the IB, ready to issue once the YIELD ceases to be blocked.
5.2 Hierarchically Programmable Scheduling
In MIPS MT, each VPE and each TC has two registers of privileged resource state associated
with its scheduling; a control register and a feedback register. The scheduling
control registers allow software to express dynamic information, such as priority or a
TDMA schedule, to a hardware scheduling policy manager, while the scheduling feedback
registers allow the scheduling hardware to provide feedback, such as the number
of instructions issued or retired by the VPE or TC.
The 34K processor core design features a modular scheduling policy manager that
can be replaced or modified to suit the quality-of-service requirements of a particular
application.
5.3 Gating Storage as a Peripheral Interface
In addition to its primary function of providing inter-thread synchronization for software,
I/O FIFOs can be mapped into the gating storage space, so that threads can be programmed
to consume or produce data in an open loop. Their execution will then be governed
by the ability of the peripherals connected to the FIFOs to consume or produce data.
6 Virtualization of MIPS MT Resources
In order to better support the portability of applications across different MIPS MT implementations,
the new user-visible resources defined by the architecture: FORKed
threads, ITC cells, and YIELD qualifiers, are all virtualizable.