Lecture Notes in Computer Science 4917

196 P. Raghavan et al.
because these transformations are not platform independent and therefore essential to
have one integrated flow. In our flow, we directly couple the Wrap-IT loop transformation
framework to the retargetable compiler, simulator and energy estimation engine.
ACE’s CoSy framework and GCC are retargetable compiler frameworks which support
a wide range of high-level compiler optimizations and code generation for a range
of processors. However, these frameworks do not support instruction set simulation and
energy aware exploration. GCC is mainly targeting code generation for general purpose
oriented processors (like x86, Alpha, PowerPC etc.) rather than for low power embedded
processors, which is our focus. The roadmap of GCC extensions indicates this is
slowly changing, e.g. providing support for loop transformations and vectorization. In
our future work we will be investigating the possibility of integrating our energy aware
exploration framework and our backend compilation framework with GCC. Although
the CoSy framework targets low power embedded processors, the scope of retargetability
is limited.
The proposed framework combines the benefits of all the above frameworks, while
giving fast estimates of energy and performance early in the design. It also provides
a framework which can analyze the impact of high level code transformations on the
architecture’s performance and power consumption. This framework can be used to
explore hw/sw co-design, architectural optimizations or software optimizations.
3 Compiler and Simulator Flow
Figure 1 shows the retargetable compiler and simulator framework. For a given application
and a machine configuration, the flow is automated to a large extent, requiring
minimal designer intervention. Manual steps are only needed for inserting specific intrinsics
from the intrinsic library or in the case of specifiying a particular loop transformation.
Since the framework is retargetable, it facilitates exploring different machine
configurations for a given application.
The loop transformation engine is part of the Wrap-IT/Uruk framework [6], which is
integrated into the tool chain (shown in Figure 1) and forms the first part of the proposed
flow. Essentially, this engine creates a polyhedral model of the application, which enables
automating the loop transformations. The compiler and the simulation framework
are built on top of Trimaran [1], but are heavily extended in order to support a wider
range of target architectures and to perform energy estimation. The integrated and extended
flow forms the COFFEE framework, as described in the following subsections.
The application code is presented to the flow as ANSI-C code. A user-friendly XML
schema is used to describe the target architecture (machine description). It is read in
by processor aware parts of the flow, e.g. the compiler (Coffee-Impact, Coffee-Elcor),
simulator (Coffee-Simulator) and power estimator. The application code can be transformed
by the Uruk front-end, before it is passed on to the rest of the compiler and
eventually used for simulation. The simulator generates detailed trace files to track the
activation of the components of the processor. These are finally processed by power and
performance estimation.
The compiler and simulator have been extended to support exploration of the following
architectural features: