Lecture Notes in Computer Science 4917

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CLI as an Effective Deployment Format for Embedded Systems 139 Fig. 3. Native code size (config. a) wrt. CLI .Leftbarisx86 ,rightbarisSH-4 . Table 3. Performance results on x86 and SH-4 (in seconds) x86 SH-4 benchmark a b c a b c ac3 0.17 0.18 0.19 0.68 0.71 0.71 adpcm 0.04 0.04 0.04 0.16 0.17 0.17 adpcmc 0.07 0.07 0.06 0.27 0.27 0.27 render 2.15 1.97 2.08 9.87 8.85 8.86 compress 0.03 0.03 0.03 0.50 0.48 0.47 crypto 0.12 0.14 0.15 0.52 0.51 0.53 dijkstra 0.20 0.22 0.22 1.32 1.34 1.34 ft 0.35 0.35 0.29 2.64 2.44 2.62 g721c 0.47 0.46 0.48 1.86 1.66 1.69 g721d 0.43 0.46 0.42 1.54 1.73 1.64 ks 28.00 29.27 30.32 123.44 144.04 140.27 mp2avswitch 2.55 2.55 2.67 12.09 11.55 11.78 mp4dec 0.05 0.06 0.06 0.33 0.35 0.34 mpeg1l2 0.67 0.64 0.63 1.77 1.96 1.95 mpeg2enc 0.76 0.50 0.79 3.37 3.50 4.19 divx 0.39 0.41 0.41 1.27 1.25 1.25 sha 0.30 0.30 0.37 1.98 2.17 2.17 video 0.10 0.10 0.10 0.36 0.37 0.37 yacr2 0.67 0.65 0.70 3.16 3.18 3.08 bitcount 0.03 0.03 0.03 0.13 0.11 0.11 cjpeg 1.72 1.72 1.70 7.73 7.53 7.80 tjpeg 0.48 0.44 0.45 3.05 2.90 3.02 crc32 0.57 0.58 0.55 1.53 1.48 1.52
140 M. Cornero et al. x86 SH-4 Fig. 4. Impact on performance of the CLI based compilation (config a vs. b) introduction of SH-4 nops to ensure proper alignment of basic blocks and functions, required to achieve high performance of this architecture. The worst case comes from the benchmark video, whereCLI is roughly 74% larger than x86 or SH-4: two thirds of the CLI code is made of initializers of arrays of bitfields, for which we emit very naive code, one bitfield at a time. A smarter code emission (which we have planned, but not yet implemented) will combine bitfields to generate the values in-place, getting rid of most initializers. Excluding the pathological cases, video for both architectures and mpeg2enc for SH-4, theSH-4 (resp. x86) is 19% (resp. 2%) larger than CLI . There are other opportunities for improvements: in some cases, we have to generate data segments for both little-endian and big-endian architectures. It is likely that, at deployment-time, the endianness is known 2 .Inthiscase,theuseless data definition could be dropped. Another reduction can come from the fact that CLI retains all the source code function and type names in the metadata. In the absence of reflection, which is true for the C language, those names can be changed to much shorter ones. Using only lower case and upper case letters, digits and underscore, one can encode (2 × 26 + 10 + 1) 2 = 5329 names on two characters, drastically reducing the size of the string pool. Our experiments confirm a previous result [6] that CLI is quite compact, similar to x86 and roughly 20% smaller (taking into account the preceding remarks) than SH-4, both notoriously known for having dense instruction sets. On the performance side, consider the Figure 4 which represents the performance of the binaries generated by the configuration b (through CLI ,at-O2) with respect to a (classical flow also at -O2). It measures the impact on performance of using the intermediate representation. The code generated through CLI in configuration b is, on average, barely slower than a. Inotherwords,using -O2 optimization level in all cases causes a 1.5% performance degradation on x86 and 0.6% on SH-4. The worst degradation is also contained, with -18% for crypto on x86 and -17% for ks on SH-4. 2 Some platforms are made of processors of both endiannesses. It could be advantageous to migrate the code from one to another and thus to keep both definitions.
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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Normalized Cycle Count 1.00 0.90 0.
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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Turbo-ROB: A Low Cost Checkpoint/Re
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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268 P. Akl and A. Moshovos 80% 70%
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270 P. Akl and A. Moshovos 25% 20%
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272 P. Akl and A. Moshovos [4] Burg
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274 A. García et al. execution tim
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276 A. García et al. whenever LPA
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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References Compiler Techniques for
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400 Author Index Shajrawi, Yousef 3
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