Lecture Notes in Computer Science 4917

88 J. Govers et al.
Table 1. Average Load and Power Consumption of Reference Processor
Active
ACQ1
Idle fclk Power Energy
[Cycles/bit] [Cycles/bit] [MHz] [mW] [nJ/bit]
4 51.7 0.3 260 53 10.5
8 83.7 0.3 210 55 22.0
16 145.0 3.0
ACQ2
185 64 50.9
4 53.3 0.7 270 54 10.7
8 86.0 2.0 220 56 22.3
16 148.0 4.0
EOP
190 64 50.8
4 22 1 115 21 4.2
8 22 2 60 13 5.2
16 22 2
DATA
30 7 5.7
4 15 1 80 15.9 3.2
8 15 1 40 8.4 3.4
16 15 1 20 5.3 4.2
Ncpb
Ncpb
Ncpb
Ncpb
Leakage 0.94mW
Furthermore we see in Fig. 3 that 37% of the total power is consumed by the program
memory and 49% of the total power is consumed by SIMD operations. Therefore it is
of interest to reduce these two components. Note that different modes show a similar
partitioning of the power consumption. Before we improve the processor we first state
a number of possible optimization steps in Sect. 4 and then apply these in Sect. 5.
4 Optimizing for Power Reduction
This section contains a number of options to reduce the power.
4.1 Reduction of the Instruction Word Size
It is possible to reduce the instruction word (IW) size by:
1. Reduction of the number of words in register files (RF). Each RF is controlled
directly from the IW, therefore smaller RFs require a smaller IW. The reduction in
IW size is only logarithmic with respect to the reduction in RF words.
2. Removing unnecessary operations, functional units or issue slots (IS). The reduction
in IW size is only logarithmic with respect to the number of removed operations.
This also has the advantage that the total hardware size is reduced.
3. Reduction of immediate size. Immediates require many bits in the IW, which are
not efficiently used [6]. The reduction in immediate bits is directly reflected in the
reduction of IW bits.