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Lecture Notes in Computer Science 4917

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Code Arrangement of Embedded Java Virtual Mach<strong>in</strong>e for NAND Flash Memory 381<br />

Embedded<br />

Caffe<strong>in</strong>e Mark<br />

J2ME API<br />

K Virtual Mach<strong>in</strong>e (KVM) 1.1<br />

uCl<strong>in</strong>ux Kernel<br />

GDB 5.0/ARMulator<br />

W<strong>in</strong>dows/Cygw<strong>in</strong><br />

Java / RAM<br />

ARM7 / FLASH<br />

ARM7 / ROM<br />

Intel X86<br />

Fig. 10. Hierarchy of simulation environment<br />

There are only two k<strong>in</strong>ds of NAND flash commodities <strong>in</strong> the market: 512-bytes<br />

and 2048-bytes per page. In this experiment, we setup the cache simulator to meet the<br />

follow<strong>in</strong>g conditions:<br />

1. There were four NAND flash page size options: 512, 1024, 2048 and 4096.<br />

2. The page replacement policy was full associative, and it is a FIFO cache.<br />

3. The number of cache memory blocks varied from 2, 4… to 32.<br />

We tuned four versions of KVM us<strong>in</strong>g the optimization process described <strong>in</strong> §5;<br />

each version suited to one k<strong>in</strong>d of page size. All the experimental measurements are<br />

compared with those from the orig<strong>in</strong>al KVM. Table 1 is the highlight of experimental<br />

results and shows the degrees of improvement of the optimized versions as well.<br />

In the test case with 4KB/512-bytes per page, the cache miss rate of the tuned<br />

KVM dropped to less than 1%, but the cache miss rate of the orig<strong>in</strong>al KVM is greater<br />

than 3% at the same condition. In the best case, the cache miss rate of the tuned KVM<br />

was 96% lower than the value from the orig<strong>in</strong>al one. Besides, <strong>in</strong> the case with only<br />

two cache blocks (1KB/512-bytes per page), the improvement was about 50%. It<br />

means tuned KVMs outperformed on devices with limited cache blocks.<br />

Normalized Page Fault Rate<br />

1.2<br />

1<br />

0.8<br />

0.6<br />

0.4<br />

0.2<br />

512<br />

1024<br />

2048<br />

4096<br />

0<br />

1024 5120 9216 13312 17408 21504 25600 29696<br />

Cache Memory Size<br />

Title Version<br />

arm-elf-b<strong>in</strong>util 2.15<br />

arm-elf-gcc 3.4.3<br />

uClibc 0.9.18<br />

J2ME (KVM) CLDC 1.1<br />

elf2flt 20040326<br />

Fig. 11. The chart of normalized cache-miss rates. The x-axis is the total size of the cache<br />

memory ( number_of_blocks * block_size ).

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