Lecture Notes in Computer Science 4917

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CLI as an Effective Deployment Format for Embedded Systems 137 – configuration c: CtoCLI , -O2 optimization level, followed by CLI to native, -O0 optimization level for GIMPLE passes and -O2 for RTL ones. This is still a CLI -based compilation flow, in which optimizations at GIMPLE level are skipped in the final compilation step. Even though it seems a bit contorted, this setup is important to evaluate up to which degree high-level optimizations can be performed only in the first step. As a matter of fact, in dynamic environments the second compilation step may be replaced by justin-time compilation, which is typically more time constrained and is likely to apply only target-specific optimizations. The benchmarks come from several sources: MediaBench [16] and MiBench [11], others are internally developed. We focused on applications or computational kernels that are relevant to our field (audio, video, cryptography, etc.) We also had to eliminate some benchmarks that had execution times close to the resolution of the timer and thus were not reliable. Table 1 gives the list of benchmarks along with a short description. Table 1. Benchmarks used in our experiments benchmark description benchmark description ac3 AC3audiodecoder mp4dec MPEG4 decoder adpcm ADPCM decoder mpeg1l2 MPEG1 audio layer 2 decoder adpcmc ADPCM encoder mpeg2enc MPEG2 encoder render image rendering pipeline divx DivX decoder compress Unix compress utility sha Secure Hash Algorithm crypto DES, RSA and MD5 video video player dijkstra shortest path in network yacr2 channel routing ft minimum spanning tree bitcount count bits in integers g721c G721 encoder cjpeg JPEG encoder g721d G721 decoder tjpeg optimized for embedded ks graph partitioning crc32 32-bit CRC polynomial mp2avswitch MPEG2 intra loop encoder + MPEG1 layer 2 audio encoder We ran our experiments on two targets. The first one is an PC Intel Pentium III clocked at 800 MHz, with 256 Mbytes of RAM, running Linux 2.6. The second one is a board developed by STMicroelectronics named STb7100 [24]. The host processor is a SH-4 clocked at 266 MHz. It features a 64-Mbits flash memory and 64-Mbytes of DDR RAM. The board itself is actually a complete solution singlechip, low-cost HD set-top box decoder for digital TV, digital set-top box or cable box. However, in these experiments we only take advantage of the host processor. 3.2 Experiments To evaluate the relevance of the CLI as a deployment format, we ran two experiments. The first one evaluates the size of the code that needs to be shipped on a device: on one hand the CLI file, on the other hand the respective native
138 M. Cornero et al. Table 2. Code size results for CLI , x86 and SH-4 (in bytes) CLI x86 SH-4 benchmark size size % size % ac3 86016 63381 -26.3% 66407 -22.8% adpcm 8704 11160 28.2% 13974 60.5% adpcmc 8704 10943 25.7% 13621 56.5% render 144384 114988 -20.4% 122232 -15.3% compress 16384 18555 13.3% 23567 43.8% crypto 73216 80796 10.4% 87040 18.9% dijkstra 7680 11208 45.9% 13990 82.2% ft 18944 21359 12.7% 23868 26.0% g721c 19456 18226 -6.3% 21392 10.0% g721d 19456 18159 -6.7% 21321 9.6% ks 16896 16196 -4.1% 22034 30.4% mp2avswitch 272384 202446 -25.7% 198486 -27.1% mp4dec 67584 53824 -20.4% 57636 -14.7% mpeg1l2 104960 86279 -17.8% 84863 -19.1% mpeg2enc 88576 85415 -3.6% 185632 109.6% divx 67584 49134 -27.3% 55869 -17.3% sha 7680 10960 42.7% 13858 80.4% video 1036288 275819 -73.4% 264067 -74.5% yacr2 37376 34441 -7.9% 39653 6.1% bitcount 9728 12678 30.3% 15912 63.6% cjpeg 226304 153161 -32.3% 158330 -30.0% tjpeg 54272 52826 -2.7% 56682 4.4% crc32 8704 10794 24.0% 13428 54.3% average -1.8% 18.9% binaries. In Table 2, the second column gives the size of the CLI executable. The following two columns give the size of the x86 binary, in absolute value, and as a percentage of the CLI . The respective numbers for SH-4 are given in the last two columns. Those numbers are graphically represented on Figure 3, left bar for x86 and right bar for SH-4. The second experiment is about performance. Since we break the compilation flow, one might expect that the compiler loses information in the back-end, and thus performance. Table 3 shows the execution times (in seconds, averaged over five runs) of our set of benchmarks compiled with the three compilation flows for x86 and SH-4. 3.3 Analysis The first comment we make on code size is that, even though x86 and SH-4 have quite dense instruction sets, the CLI binary is often smaller. The case of mpeg2enc on SH-4 is extreme and comes from the fact that the native compiler decided to statically link part of the math library to take advantage of specialized trigonometric routines. Several benchmarks see their code size increased by the
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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Architecture Enhancements for the A
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Implementation of an UWB Impulse-Ra
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Implementation of an UWB Impulse-Ra
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Drug Design Issues on the Cell BE 1
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Drug Design Issues on the Cell BE 1
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Normalized Cycle Count 1.00 0.90 0.
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Integrated CPU Cache Power Manageme
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Variation-Aware Software Techniques
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Average leakage-power saving (%) Va
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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Turbo-ROB: A Low Cost Checkpoint/Re
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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266 P. Akl and A. Moshovos throttli
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268 P. Akl and A. Moshovos 80% 70%
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270 P. Akl and A. Moshovos 25% 20%
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272 P. Akl and A. Moshovos [4] Burg
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274 A. García et al. execution tim
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276 A. García et al. whenever LPA
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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Complementing Missing and Inaccurat
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Using Dynamic Binary Instrumentatio
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L1 D-Cache Miss Rate (%) CPI 5 4 3
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CPI Error (%) 10 5 0 -5 -10 FP Resu
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CPI Error (%) 40 30 20 10 0 Using D
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References Compiler Techniques for
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Code Arrangement of Embedded Java V
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Aggressive Function Inlining: Preve
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400 Author Index Shajrawi, Yousef 3
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