Lecture Notes in Computer Science 4917

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60 R. Chaves et al. the coprocessor architectural paradigm, allowing the usage of reconfigurable custom designed hardware units. In this computational approach, the non critical part of the software code is executed on a General Purpose Processor (GPP), while the main DES algorithm, is executed on the Custom Computing Unit (CCU). The DES core is seen by the programmer in the same manner as a software implemented function. The decision where the function is executed is made at compile time. At microarchitectural level the arbiter, depicted in Figure 7, redirects each instruction either to the GPP (a PowerPC in our case) or to the cryptographic units. 64 64 Load Round MUX Address & Data Data KEY_IN MUX_C SHIFTER_C Current_KEY 64 PC-1 24 24 PC-2 48 MUX_D SHIFTER_D Fig. 6. DES key expansion Main Memory Memory selection Key expansion DES Instructions ARBITER Address Start /Stop 32 HALT Address & Data Control Unit DES core PowerPC Register File Address & Data 32 Load Round Fig. 7. Polymorphic processor internal structure XREG
BRAM-LUT Tradeoff on a Polymorphic DES Design 61 In a software function, the parameter passing is done through the stack. In the Molen processor, when a hardware function is invoked the parameters are passed through a dedicated register bank, designated by eXchange REGisters (XREG). Given that the dedicated computational units are also connected to the main data memory, only initialization parameters are passed to the DES computational unit via the XREG. These parameter are the private key, memory pointers to the data to be ciphered, and the operation modes, e.g. encrypt or decrypt. The data to be processed is directly retrieved and send to the main data memory, via a shared memory mechanism. In order to illustrate the data flow, the encryption operation for a 64 bit data block is described. When the DES cipher function is called, a few software instructions are executed, namely instructions that move the function parameters from the GPP internal registers to the XREG, followed by an execute instruction. When an execute instruction is detected by the arbiter, the later starts addressing the microcode memory, giving control of the data memory to the DES core, and signals it to start the computation via the start signal depicted in Figure 7. Once the DES core receives the start signal, it starts retrieving the values from the XREG. The first value read is the operation mode, which indicates which operation will be performed. Continuously, the start and end memory addresses for the data to cipher are retrieved from the XREG. While the first data block is read from the memory, the key is read from the XREG and stored in the DES internal registers. After this initialization phase, the DES core enters a loop where, while the data is being ciphered, the next 64-bit data block is read from the memory. In the end of each loop, the ciphered data is written back into the data memory. When the current memory address coincides with the data end address, the computation loop is broken and the stop signal is sent to the arbiter. Upon receiving this stop signal, the arbiter returns the memory control to the GPP. To indicate which function performs the DES encryption computed in hardware, a pragma annotation is used in the C code, as depicted in Figure 8. #pragma DES DES (key, &data[0], &data[end], mode){ \∗ implemented in HW ∗\ } Fig. 8. Usage of the pragma notation This pragma annotation is recognized by the compiler which automatically generates the required instructions sequence [4]. This pragma addition and recompilation are the only operation required to use the hardware implemented DES, instead of the software implemented version. With this mechanism, any application using DES or 3DES can be accelerated by the DES core, with a reduced time market and a very low development cost. 5 Performance Analysis To evaluate the advantages and disadvantages of using BRAMs on DES computational structures and the polymorphic DES implementation, a Xilinx VIRTEX II Pro 30
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
Page 17 and 18: MIPS MT: A Multithreaded RISC Archi
Page 19 and 20: 2.2 VPEs as Scheduling Domains MIPS
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Page 23 and 24: 6.1 Thread Context Virtualization M
Page 25 and 26: 8 Experimental Results MIPS MT: A M
Page 27 and 28: Cycles/ Iteration MIPS MT: A Multit
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Page 40 and 41: speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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Page 48 and 49: Modeling Multigrain Parallelism on
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Fast Bounds Checking Using Debug Re
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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avg normalized execution time 1.000
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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speed-up 8 6 4 2 0 FFT3D 256 64-A F
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Normalized Cycle Count 1.00 0.90 0.
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Integrated CPU Cache Power Manageme
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Variation-Aware Software Techniques
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Average leakage-power saving (%) Va
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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Turbo-ROB: A Low Cost Checkpoint/Re
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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266 P. Akl and A. Moshovos throttli
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268 P. Akl and A. Moshovos 80% 70%
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270 P. Akl and A. Moshovos 25% 20%
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272 P. Akl and A. Moshovos [4] Burg
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274 A. García et al. execution tim
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276 A. García et al. whenever LPA
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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Complementing Missing and Inaccurat
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6.1 Filling Edge Profile from Verte
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Using Dynamic Binary Instrumentatio
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L1 D-Cache Miss Rate (%) CPI 5 4 3
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CPI Error (%) 10 5 0 -5 -10 FP Resu
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CPI Error (%) 40 30 20 10 0 Using D
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Phase Complexity Surfaces: Characte
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Compiler Techniques for Reducing Da
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References Compiler Techniques for
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Code Arrangement of Embedded Java V
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Aggressive Function Inlining: Preve
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400 Author Index Shajrawi, Yousef 3
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