Lecture Notes in Computer Science 4917

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Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array 75 Energy (mJ) Energy (mJ) 0.065 0.060 0.055 0.050 0.045 0.040 0.035 arch_5 arch_4_pb arch_4 arch_2 arch_7 arch_7_pb arch_5_pb arch_3 arch_8 arch_2_pb arch_6 arch_3_pb arch_6_pb arch_1 arch_1_pb 0.030 500 550 600 650 700 750 800 850 900 950 Simulation Time (us) 1.0E-03 9.5E-04 9.0E-04 Fig. 9. IDCT Energy-Delay @ 100MHz arch_1_pb 8.5E-04 arch_5 8.0E-04 arch_7 7.5E-04 7.0E-04 6.5E-04 6.0E-04 arch_6 arch_7_pb arch_4_pb arch_4 arch_2 arch_6_pb arch_3_pb arch_2_pb arch_5_pb arch_1 arch_3 5.5E-04 5.0E-04 arch_8 7 9 11 13 15 17 19 21 23 Simulation Time (us) Fig. 10. FFT Energy-Delay @ 100MHz Table 3. Base vs. arch 8 for IDCT & FFT @ 100MHz MIPS/mW mW/MHz Power Energy Area Benchmark (mW) (uJ) mm 2 IDCT base 17.51 0.81 80.45 37.72 1.59 arch 8 20.00 0.63 62.68 37.46 1.36 Improvement 14.22% 22% 22% 0.6% 14.4% FFT base 9.40 0.72 73.28 0.62 arch 8 10.95 0.57 57.05 0.61 Improvement 16.5% 20.8% 22.1% 1.6%
76 F. Bouwens et al. fixed at 64 words. The global DRF has 8 read and 4 write ports, which are 32-bits wide. The global PRF has 4 read and write ports each 1-bit wide. The results in Table 4 show that 4 registers provide the least amount of instructions and cycles with an optimal instructions per cycle (IPC) for an 4x4 array. The registers that are not used will be clock gated reducing the negative impact on power. Interesting to note is the decrease of IPC with increasing RF sizes. This was unexpected as IPC usually saturates with increasing RF sizes. Nevertheless, our tests showed that the scheduler of DRESC2.x improved over time [9] as the IPC increased with better usage of the local DRFs, but the number of utilized registers is still relatively low. Reg_con_shared_2R_1W_morphosys RF VLIW DRF FU FU FU FU RF RF FU FU FU FU FU FU FU FU RF FU FU FU FU Fig. 11. Proposed ADRES architecture with shared RFs 5 Final Results Table 4. Reducing Register File Size arch 8 Local Register File Size Application 2 4 8 16 IDCT Instructions 974632 923940 923980 923960 Cycles 62924 59755 59762 59757 IPC 9.69 10.21 10.21 10.21 FFT Instructions 11364 10532 11040 11060 Cycles 1087 1035 1063 1065 IPC 2.48 2.73 2.57 2.58 The optimizations in Sections 4.1 till 4.3 led to arch 8 architecture with shared local DRFs, Morphosys interconnections and reduced RF sizes. The architecture discussed is a non-pipelined version with no further optimizations of the architecture and data path. We apply three additional optimizations for the architecture and data path in this section: clock gating, operand isolation and pipelining. Clock gating targets the register files by reducing their switching activity. This feature is implemented automatically by Synopsys Power Compiler. Empirical results show a power reduction of the register file between 50 - 80%. A pipelined version of the same architecture shows 20 - 25% power improvement in overall. Operand Isolation targets the data path of a FU reducing switching activity of unused components. It is implemented manually as the automated version built in the design tools used only reduced the power by 1%. Our manual implementation using OR-based isolation [12] reduced power by 30% for a single FU and 30 - 40% for the overall pipelined system. Pipelining increases performance significantly by creating shorter critical paths and provides higher throughput. Pipelining, which is implemented by hand, has a disadvantage that power increases linearly when increasing the frequency unless clock gating and operand isolation is used. These optimizations are most efficient with multi-cycle architectures and very suitable for pipelined architectures.
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Integrated CPU Cache Power Manageme
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Variation-Aware Software Techniques
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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Turbo-ROB: A Low Cost Checkpoint/Re
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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268 P. Akl and A. Moshovos 80% 70%
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270 P. Akl and A. Moshovos 25% 20%
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272 P. Akl and A. Moshovos [4] Burg
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276 A. García et al. whenever LPA
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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Using Dynamic Binary Instrumentatio
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References Compiler Techniques for
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Code Arrangement of Embedded Java V
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400 Author Index Shajrawi, Yousef 3
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