Lecture Notes in Computer Science 4917

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318 V.M. Weaver and S.A. McKee Overall, these tools show great promise in encouraging use of SimPoint for architectural studies. Our tools make generating simulation points fast and easy, and will help others in generating more accurate results in their experiments. Acknowledgments This material is based upon work supported by the National Science Foundation under Grants 0509406, 0444413, and 0325536. References 1. Austin, T.: Simplescalar 4.0 release note http://www.simplescalar.com/ 2. Bellard, F.: Qemu, a fast and portable dynamic translator. In: Proc. 2005 USENIX Annual Technical Conference, FREENIX Track, pp. 41–46 (April 2005) 3. Buck, B., Hollingsworth, J.: An API for runtime code patching. The International Journal of High Performance Computing Applications 14(4), 317–329 (2000) 4. Burger, D., Austin, T.: The simplescalar toolset, version 2.0. Technical Report 1342, University of Wisconsin (June 1997) 5. Eranian, S.: Perfmon2: A flexible performance monitoring interface for Linux. In: Proc. of the 2006 Ottawa Linux Symposium, pp. 269–288 (July 2006) 6. KleinOsowski, A., Lilja, D.: MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research. Computer Architecture Letters 1 (June 2002) 7. Luk, C.-K., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V., Hazelwood, K.: Pin: Building customized program analysis tools with dynamic instrumentation. In: Proc. ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 190–200 (June 2005) 8. Nagpurkar, P., Krintz, C.: Visualization and analysis of phased behavior in Java programs. In: Proc. ACM 3rd international symposium on Principles and practice of programming in Java, pp. 27–33 (2004) 9. Nethercote, N., Seward, J.: Valgrind: A framework for heavyweight dynamic binary instrumentation. In: Proc. ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 89–100 (June 2007) 10. Patil, H., Cohn, R., Charney, M., Kapoor, R., Sun, A., Karunanidhi, A.: Pinpointing representative portions of large Intel Itanium programs with dynamic instrumentation. In: Proc. IEEE/ACM 37th Annual International Symposium on Microarchitecture, pp. 81–93 (December 2004) 11. Perelman, E., Hamerly, G., Calder, B.: Picking statistically valid and early simulation points. In: Proc. IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques, pp. 244–256 (September 2003) 12. Sherwood, T., Perelman, E., Calder, B.: Basic block distribution analysis to find periodic behavior and simulation points in applications. In: Proc. IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques, pp. 3–14 (September 2001) 13. Sherwood, T., Perelman, E., Hamerly, G., Calder, B.: Automatically characterizing large scale program behavior. In: Proc. 10th ACM Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 45–57 (October 2002)
Using Dynamic Binary Instrumentation 319 14. Srivastava, A., Eustace, A.: ATOM: A system for building customized program analysis tools. In: Proc. ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 196–205 (June 1994) 15. Standard Performance Evaluation Corporation. SPEC CPU benchmark suite (2000), http://www.specbench.org/osg/cpu2000/ 16. Standard Performance Evaluation Corporation. SPEC CPU benchmark suite (2006), http://www.specbench.org/osg/cpu2006/ 17. Wunderlich, R., Wenish, T., Falsafi, B., Hoe, J.: SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling. In: Proc. 30th IEEE/ACM International Symposium on Computer Architecture, pp. 84–95 (June 2003) 18. Yi, J., Kodakara, S., Sendag, R., Lilja, D., Hawkins, D.: Characterizing and comparing prevailing simulation techniques. In: Proc. 11th IEEE Symposium on High Performance Computer Architecture, pp. 266–277 (February 2005)
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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Architecture Enhancements for the A
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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speed-up 8 6 4 2 0 FFT3D 256 64-A F
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Normalized Cycle Count 1.00 0.90 0.
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Integrated CPU Cache Power Manageme
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Variation-Aware Software Techniques
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Average leakage-power saving (%) Va
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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Code Arrangement of Embedded Java V
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Aggressive Function Inlining: Preve
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400 Author Index Shajrawi, Yousef 3
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