Lecture Notes in Computer Science 4917

More documents

Recommendations

Info

Studying Compiler Optimizations on Superscalar Processors 129 4. Taha, T.M., Wills, D.S.: An instruction throughput model of superscalar processors. In: RSP, pp. 156–163 (2003) 5. Michaud, P., Seznec, A., Jourdan, S.: Exploring instruction-fetch bandwidth requirement in wide-issue superscalar processors. In: Malyshkin, V. (ed.) Parallel Computing Technologies. LNCS, vol. 1662, pp. 2–10. Springer, Heidelberg (1999) 6. Riseman, E.M., Foster, C.C.: The inhibition of potential parallelism by conditional jumps. IEEE Transactions on Computers C-21, 1405–1411 (1972) 7. Wall, D.W.: Limits of instruction-level parallelism. In: ASPLOS, pp. 176–188 (1991) 8. Chou, Y., Fahs, B., Abraham, S.: Microarchitecture optimizations for exploiting memorylevel parallelism. In: ISCA, pp. 76–87 (2004) 9. KleinOsowski, A.J., Lilja, D.J.: MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research. Computer Architecture Letters 1, 10–13 (2002) 10. Burger, D.C., Austin, T.M.: The SimpleScalar Tool Set. Computer Architecture News (1997), See also http://www.simplescalar.com 11. Valluri, M.G., Govindarajan, R.: Evaluating register allocation and instruction scheduling techniques in out-of-order issue processors. In: Malyshkin, V. (ed.) Parallel Computing Technologies. LNCS, vol. 1662, pp. 78–83. Springer, Heidelberg (1999) 12. Silvera, R., Wang, J., Gao, G.R., Govindarajan, R.: A register pressure sensitive instruction scheduler for dynamic issue processors. In: Malyshkin, V. (ed.) Parallel Computing Technologies. LNCS, vol. 1277, pp. 78–89. Springer, Heidelberg (1997) 13. Pai, V.S., Adve, S.V.: Code transformations to improve memory parallelism. In: MICRO, pp. 147–155 (1999) 14. Holler, A.M.: Optimization for a superscalar out-of-order machine. In: MICRO, pp. 336–348 (1996) 15. Cohn, R., Lowney, P.G.: Design and analysis of profile-based optimization in Compaq’s compilation tools for Alpha. Journal of Instruction-Level Paralellism 3, 1–25 (2000) 16. Vaswani, K., Thazhuthaveetil, M.J., Srikant, Y.N., Joseph, P.J.: Microarchitecture sensitive empirical models for compiler optimizations. In: CGO, pp. 131–143 (2007)
An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems ⋆ Marco Cornero, Roberto Costa, Ricardo Fernández Pascual ⋆⋆ , Andrea C. Ornstein, and Erven Rohou STMicroelectronics Advanced System Technology Via Cantonale 16E 6928 Manno (Switzerland) Abstract. Software productivity for embedded systems is greatly limited by the fragmentation of platforms and associated development tools. Platform virtualization environments, like Java and Microsoft .NET, help alleviate the problem, but they are limited to host functionalities running on the system microcontroller. Due to the ever increasing demand for processing power, it is desirable to extend their benefits to the rest of the system. We present an experimental framework based on GCC that validates the choice of CLI as a suitable processor-independent deployment format. In particular, we illustrate our GCC port to CLI and we evaluate the generated bytecode in terms of code size and performance. We inject it back into GCC through a CLI front-end that we also illustrate, and we complete the compilation down to native code. We show that using CLI does not degrade performance. Compared to other CLI solutions, we offer a full development flow for the C language, generating a subset of pure CLI that does not require any virtual machine support other than a JIT compiler. It is therefore well suited for deeply embedded media processors running high performance media applications. Keywords: Common Language Infrastructure, embedded systems, deployment, GCC. 1 Introduction The productivity of embedded software development is heavily limited by several factors, the most important being the high fragmentation of the hardware platforms combined with the multiple target operating systems and associated tools. Indeed, in order to reach a wide customer base, software developers need to port, test and maintain their applications to tens of different configurations, wasting a great deal of effort in the process. Platform virtualization technologies have been very successful in alleviating this problem, as it is evident by the ⋆ This work was partially funded by the HiPEAC Network of Excellence. ⋆⋆ This author performed this work as a HiPEAC PhD student at STMicroelectronics. P. Stenström et al. (Eds.): HiPEAC 2008, LNCS 4917, pp. 130–144, 2008. c○ Springer-Verlag Berlin Heidelberg 2008
Page 1 and 2:
Lecture Notes in Computer Science 4
Page 3 and 4:
Volume Editors Per Stenström Chalm
Page 5 and 6:
VI Preface The planning of a confer
Page 7 and 8:
VIII Organization Mahmut Kandemir P
Page 9 and 10:
Invited Program Table of Contents S
Page 11:
Table of Contents XIII Turbo-ROB: A
Page 14 and 15:
4 M. Valero and J. Labarta future s
Page 17 and 18:
MIPS MT: A Multithreaded RISC Archi
Page 19 and 20:
2.2 VPEs as Scheduling Domains MIPS
Page 21 and 22:
MIPS MT: A Multithreaded RISC Archi
Page 23 and 24:
6.1 Thread Context Virtualization M
Page 25 and 26:
8 Experimental Results MIPS MT: A M
Page 27 and 28:
Cycles/ Iteration MIPS MT: A Multit
Page 29:
9 Conclusions MIPS MT: A Multithrea
Page 32 and 33:
MPI: Message Passing on Multicore P
Page 34 and 35:
Page 36 and 37:
Page 38 and 39:
overhead per word (cycles) 1200 100
Page 40 and 41:
speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
Page 42 and 43:
speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
Page 44 and 45:
Page 46 and 47:
Page 48 and 49:
Modeling Multigrain Parallelism on
Page 50 and 51:
Page 52 and 53:
Page 54 and 55:
Page 56 and 57:
Page 58 and 59:
Page 60 and 61:
Page 63 and 64:
BRAM-LUT Tradeoff on a Polymorphic
Page 65 and 66:
32 L0 L1 BRAM-LUT Tradeoff on a Pol
Page 67 and 68:
Page 69 and 70:
Page 71 and 72:
Page 73:
Page 76 and 77:
Architecture Enhancements for the A
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
Page 88 and 89: Architecture Enhancements for the A
Page 90 and 91: Architecture Enhancements for the A
Page 92 and 93: Implementation of an UWB Impulse-Ra
Page 107 and 108: Fast Bounds Checking Using Debug Re
Page 121: Fast Bounds Checking Using Debug Re
Page 124 and 125: Studying Compiler Optimizations on
Page 130 and 131: avg normalized execution time 1.000
Page 140 and 141: CLI as an Effective Deployment Form
Page 155 and 156: Compilation Strategies for Reducing
Page 167 and 168: 180% 160% 140% 120% 100% 80% 60% 40
Page 169 and 170: Experiences with Parallelizing a Bi
Page 183: Experiences with Parallelizing a Bi
Page 186 and 187: Drug Design Issues on the Cell BE 1
Page 188 and 189:
Drug Design Issues on the Cell BE 1
Page 190 and 191:
Page 192 and 193:
Page 194 and 195:
speed-up 8 6 4 2 0 FFT3D 256 64-A F
Page 196 and 197:
Page 198 and 199:
Page 201 and 202:
COFFEE: COmpiler Framework for Ener
Page 203 and 204:
Page 205 and 206:
Benchmark Source Code * transformed
Page 207 and 208:
Page 209 and 210:
RTL for each Component * Gate−lev
Page 211 and 212:
Page 213 and 214:
Normalized Cycle Count 1.00 0.90 0.
Page 215 and 216:
Page 217 and 218:
Integrated CPU Cache Power Manageme
Page 219 and 220:
Page 221 and 222:
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231:
Page 234 and 235:
Variation-Aware Software Techniques
Page 236 and 237:
Page 238 and 239:
Page 240 and 241:
Page 242 and 243:
Page 244 and 245:
Average leakage-power saving (%) Va
Page 246 and 247:
Page 248 and 249:
Page 250 and 251:
244 Y. Sazeides et al. of mispredic
Page 252 and 253:
246 Y. Sazeides et al. Affector BB1
Page 254 and 255:
248 Y. Sazeides et al. 2.3 How to U
Page 256 and 257:
250 Y. Sazeides et al. Cumulative D
Page 258 and 259:
252 Y. Sazeides et al. ijpeg, andbo
Page 260 and 261:
254 Y. Sazeides et al. Misses/KI 12
Page 262 and 263:
256 Y. Sazeides et al. Mahlke and N
Page 265 and 266:
Turbo-ROB: A Low Cost Checkpoint/Re
Page 267 and 268:
260 P. Akl and A. Moshovos Original
Page 269 and 270:
262 P. Akl and A. Moshovos Oldest I
Page 271 and 272:
264 P. Akl and A. Moshovos new firs
Page 273 and 274:
266 P. Akl and A. Moshovos throttli
Page 275 and 276:
268 P. Akl and A. Moshovos 80% 70%
Page 277 and 278:
270 P. Akl and A. Moshovos 25% 20%
Page 279:
272 P. Akl and A. Moshovos [4] Burg
Page 282 and 283:
274 A. García et al. execution tim
Page 284 and 285:
276 A. García et al. whenever LPA
Page 286 and 287:
278 A. García et al. @12: load r2,
Page 288 and 289:
280 A. García et al. Target Loop E
Page 290 and 291:
282 A. García et al. reduction 100
Page 292 and 293:
284 A. García et al. IPC speedup 7
Page 294 and 295:
286 A. García et al. SPECfp benchm
Page 297 and 298:
Complementing Missing and Inaccurat
Page 299 and 300:
90 100 100 25 75 25 25 100 100 10 1
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
Page 307 and 308:
6.1 Filling Edge Profile from Verte
Page 309 and 310:
Page 311 and 312:
Using Dynamic Binary Instrumentatio
Page 313 and 314:
L1 D-Cache Miss Rate (%) CPI 5 4 3
Page 315 and 316:
Page 317 and 318:
Page 319 and 320:
CPI Error (%) 10 5 0 -5 -10 FP Resu
Page 321 and 322:
CPI Error (%) 40 30 20 10 0 Using D
Page 323 and 324:
Page 325:
Page 328 and 329:
Phase Complexity Surfaces: Characte
Page 330 and 331:
Page 332 and 333:
Page 334 and 335:
Page 336 and 337:
( log10) phases of Number 4.0 3.5 3
Page 338 and 339:
Page 340 and 341:
Page 343 and 344:
MLP-Aware Dynamic Cache Partitionin
Page 345 and 346:
Page 347 and 348:
Page 349 and 350:
Page 351 and 352:
Page 353 and 354:
(a) IPC as we vary the number of as
Page 355 and 356:
Page 357 and 358:
Page 359 and 360:
Compiler Techniques for Reducing Da
Page 361 and 362:
Page 363 and 364:
Page 365 and 366:
Page 367 and 368:
Page 369 and 370:
Page 371 and 372:
40 35 30 25 ) te ( % 20 -ra M is s
Page 373 and 374:
References Compiler Techniques for
Page 375 and 376:
Code Arrangement of Embedded Java V
Page 377 and 378:
Page 379 and 380:
Page 381 and 382:
Page 383 and 384:
Page 385 and 386:
Page 387 and 388:
Page 389:
Page 392 and 393:
Aggressive Function Inlining: Preve
Page 394 and 395:
f1(){ ...g();....} f2(){....q();...
Page 396 and 397:
Page 398 and 399:
Page 400 and 401:
foo:(80 times) BB1: Call bar BB2: C
Page 402 and 403:
Page 404 and 405:
Page 406:
400 Author Index Shajrawi, Yousef 3
show all

Lecture Notes in Computer Science 4917

Create successful ePaper yourself

Delete template?

Save as template?