Lecture Notes in Computer Science 4917

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Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator 259 Ideally, a GC would be allocated at every instruction such that the recovery latency is always constant. In practice, because the RAT is a performance critical structure only a limited number of GCs can be implemented without impacting the clock cycle significantly and thus reducing overall performance. For example, RAT latency increases respectively by 1.6%, 5%, and 14.4% when four, eight, and 16 GCs are used relative to a RAT with no GCs for a 512-entry window 4way superscalar processor with 64 architectural registers and for a 130nm CMOS commercial technology [12]. Recent work suggested using selective GC allocation to reduce the number of GCs necessary to maintain high performance [2,1,5,11]. Even with these advances, at least eight and often 16 GCs are needed to maintain performance within 2% of that possible with an infinite number of checkpoints allocated at all branches with a 256-entry or larger window processor. These GCs increase RAT latency and the clock cycle and thus reduce performance. Moreover, RAT GCs increase RAT energy consumption. This is undesirable as the RAT exhibits high energy density. Accordingly, methods for reducing the number of GCs or for eliminating the need for GCs altogether would lead to improved performance and avoid an increase in power density in the RAT. This work proposes Turbo-ROB,orTROB, a checkpoint recovery accelerator that can complement or replace the ROB and the GCs. The TROB is off the critical path and as a result its latency and energy can be tuned with greater flexibility. The Turbo-ROB is similar to the ROB but it requires a lot fewer entries since the TROB only stores information necessary to recover at a few selected branches, called repair points. Specifically, the TROB stores recovery information for the first update to each register after a repair point. Because programs tend to reuse registers often, many instructions are ignored by the TROB. In contrast, the ROB stores information for all instructions because it allows recovery at any instruction. While the ROB is a general mechanism that treats all recoveries as equal, the TROB is optimized for the common case of branch-related recoveries. The TROB can be used to accelerate recovery in conjunction with a ROB or GCs, or it can be used as a complete replacement for the ROB and the GCs. Unlike previous proposals for reducing the recovery latency, the Turbo-ROB does not require modifications to the RAT. This paper makes the following contributions: (1) It proposes “Turbo-ROB”, a ROB-like recovery mechanism that requires less resources than the ROB and allows faster recovery on the frequent case of control flow mis-speculations. Given that the TROB is off the critical path it alleviates some of the pressure to scale the register alias table and the re-order buffer. (2) It shows that the TROB can be used to improve performance over a ROB-only recovery mechanism. (3) It shows that the TROB can replace a ROB offering performance that is close to that possible with few GCs. Eliminating the ROB is desirable since it is an energy and latency inefficient structure [2]. (4) It shows that the TROB improves performance even when used with a GC-based recovery mechanism. More importantly, the TROB reduces GC pressure allowing implementations that use very few GCs. For example, the results of this paper demonstrate that
260 P. Akl and A. Moshovos Original Code Renamed Code A Beq R1, R4, LABEL B Sub R2, R2, R3 C Mult R3, R2, R1 D Add R2, R2, R1 E Beq R3, R4, LABEL2 Architectural Destination Register Previous RAT Map A Beq P1, P7, LABEL B Sub P3, P2, P4 C Mult P5, P3, P1 D Add P6, P3, P1 E Beq P5, P7, LABEL2 none none R2 P2 R3 P4 R2 P3 Original RAT none none R1 R2 R3 R4 Reorder Buffer 1 (A) 2 (B) 3 (C) 4(D) 5 (E) 6 Fig. 1. Given an instruction to recover at, it is not always necessary to process all subsequent instructions recorded in the ROB a TROB with one GC performs as well as an implementation that uses four GCs. A single GC RAT implementation is simpler than one that uses more GCs. The rest of this paper is organized as follows: Section 2 presents the TROB design. Section 3 reviews related work. Section 4 presents the experimental analysis of TROB. Finally, Section 5 concludes this work. In this paper we restrict our attention to recovery from control flow mispeculation. However, the TROB can also be used to recover from other exceptions such as page faults. In the workloads we study these exceptions are very infrequent. We also focus on relatively large processors with up to 512-entry instruction windows. However, we do demonstrate that the TROB is beneficial even for smaller window processors that are more representative of today’s processor designs. We note, however, that as architects are revisiting the design of large window processor simplifying the underlying structures and as multithreading becomes commonplace it is likely that future processors will use larger windows. 2 Turbo-ROB Recovery For clarity, we initially restrict our attention to using the TROB to complement a ROB recovery mechanism. In Sections 2.4 and 2.5 we discuss how the TROB can be used without a ROB or with GCs respectively. The motivation for Turbo-ROB is that not all instructions inserted in the ROB are needed for every recovery. We motivate the Turbo-ROB design by first reviewing how ROB recovery works. The ROB maintains a log of all changes in program order. Existing ROB designs allocate one entry per instruction in the window. Each ROB entry contains sufficient information to reverse the effects of the corresponding instruction. For the RAT it is sufficient to keep the architectural register name and the previous physical register it mapped to. On a mis-speculation, all ROB entries for the wrong path instructions are traversed in reverse program order. While the ROB design allows recovery at any instruction, given a specific instruction to recover at, not all ROB entries need to be traversed. Specifically, for every RAT entry, only the first corresponding ROB entry after the mispredicted branch is needed. P1 P2 P4 P7
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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Modeling Multigrain Parallelism on
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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400 Author Index Shajrawi, Yousef 3
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