Lecture Notes in Computer Science 4917

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Original Code A Beq R1, R4, LABEL B Sub R2, R2, R3 C Div R3, R2, R1 D Add R2, R2, R3 E Mult R3, R2, R3 Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator 263 Renamed Code F Beq R4, R3, LABEL2 F Beq P4, P8, LABEL2 G Div R1, R2, R3 G Div P9, P7, P8 H Add R2, R1, R1 H Add P10, P9, P9 Architectural Destination Register Previous RAT Map A Beq P1, P4, LABEL B Sub P5, P2, P3 C Div P6, P5, P1 D Add P7, P5, P6 E Mult P8, P7, P6 0 (A) 1 (B) 2 (C) ROB 3 (D) 4 (E) none none ROB Pointer Architectural Destination Register Previous RAT Map R2 P2 R2 P2 R3 P3 R3 P3 Original RAT R2 P5 R1 P1 R3 P6 R2 P7 5 (F) none none 0 1 TROB 2 3 4 1 2 6 7 6 (G) R1 P1 TROB modify flag (TM) 0 1 1 0 0 0 1 0 (A) 1 (B) 2 (C) PDRL 3 (D) 4 (E) Physical Destination Register none P5 P6 P7 P8 R1 R2 R3 R4 P1 P2 P3 P4 RAT after decoding H 5 (F) none R1 R2 P10 R3 R4 P9 P8 P4 6 (G) P9 7 (H) R2 P7 1 ARB after decoding H R1 1 R2 1 R3 0 R4 0 8 7 (H) 8 P10 Fig. 4. Example of recovery using the Turbo-ROB: repair points are initiated at instructions A and F. Recovering at A requires traversing entries 3 to 0 in the TROB. The physical register free list is recovered by traversing entries 7 to 0 in the PDRL. point. We then complete the recovery using the ROB, starting at the instruction corresponding to the repair point at which partial recovery took place. If no such repair point is found, we rely solely the ROB for recovery. Reclaiming Physical Registers: Since the TROB contains only first updates, it can’t be used to free all the physical registers allocated by wrong path instructions. We assume that the free register list (FRL) contains embedded checkpoints which are allocated at repair points. The free register list is typically implemented as a bit vector with one bit per register. Accordingly, checkpoints similar to those used for the RAT can be used here also. Since the FRL is a unidimensional structure embedding checkpoints does not impact its latency greatly as it does in the RAT. Upon commit, an instruction freeing a register, must mark it as free in the current FRL and in all active checkpoints by clearing all corresponding bits. Assuming that these bits are organized in a single SRAM column, clearing them requires extending the per column reset signal over the whole column plus a pull-down transistor per bit. 2.2 Recovery Example Figure 4 illustrates an example of recovery using the TROB. Following the decode of branch A, instructions B and C perform first updates of RAT entries R2 and R3 and allocate TROB entries 0 and 1. The ARB is reset at instruction F and new TROB entries are allocated for instructions G and H, whichperform
264 P. Akl and A. Moshovos new first updates to the RAT entries R1 and R2. IfbranchA is mispredicted, recovery proceeds in reverse order starting from the TROB head (entry 3) and until entry 0 is reached. Recovering via the ROB would require traversing seven entries as opposed to the four required by the TROB. If branch F was mispredicted, recovery would only use TROB entries 3 and 2. If instruction C raised an exception, recovery proceeds using the ROB by traversing entries 7 to 3 in reverse order. Alternatively, we could recover by first recovering at the closest subsequent repair point using the TROB (recovering at instruction F by using the TROB entries 3 and 2) and then use the ROB to complete the recovery (by using ROB entries 4 to 3). 2.3 Selective Repair Point Initiation Our baseline mechanism initiates repair points at all branches. Creating repair points less frequently reduces the space requirements for the TROB and makes TROB recovery faster. In the example shown in Figure 4, not creating a TROB repair point at branch F reduces TROB pressure since instruction H would not be saved. Since TROB entry 3 would not be utilized, repairing the RAT state using the TROB if instruction A was mispredicted would be faster. However, if F was mis-speculated then we would have to use the slower ROB to recover. To balance between decreasing the utilization and the recovery latency of the TROB on one side, and increasing the rate of slow recoveries that do not utilize solely the TROB on the other side, we can selectively create repair points at branches that are highly likely to be mispredicted. Confidence estimators dynamically identify such branches. Zero-cost confidence estimation has been show to work well with selective RAT checkpoint allocation [11]. In the rest of this study, we refer to the method that uses selective repair point initiation as sTROB. 2.4 Eliminating the ROB The TROB can be used as a complete replacement for the ROB. In one design, the TROB replaces the ROB and repair points are initiated at every branch. In this case, recovery is possible via the TROB at every branch. Other exceptions can be handled using re-execution and a copy of the RAT that is updated at commit time. This policy was suggested by Akkary et al. [2] for a design that used only GCs and no ROB. To guarantee that every branch gets a repair point we stall decode whenever the TROB is full and a new entry is needed. This design artificially restricts the instruction window. However, as we show experimentally, this rarely affects performance. Alternatively, we can allow some branches to proceed without a repair point, or to abandon the current repair point and rely instead on re-execution as done for other exceptions. In another design, the TROB replaces the ROB but repair points are initiated only on weak branches as predicted via a confidence estimation mechanism. In this design, it is not always possible to recover via the TROB. Whenever no repair point exists, we rely instead on re-execution from an earlier repair point or from the beginning of the window.
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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Architecture Enhancements for the A
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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avg normalized execution time 1.000
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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speed-up 8 6 4 2 0 FFT3D 256 64-A F
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Normalized Cycle Count 1.00 0.90 0.
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Integrated CPU Cache Power Manageme
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CPI Error (%) 40 30 20 10 0 Using D
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Using Dynamic Binary Instrumentatio
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Compiler Techniques for Reducing Da
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References Compiler Techniques for
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Code Arrangement of Embedded Java V
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Aggressive Function Inlining: Preve
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foo:(80 times) BB1: Call bar BB2: C
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400 Author Index Shajrawi, Yousef 3
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