Lecture Notes in Computer Science 4917

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374 C.–C. Lin and C.–L. Chen of demonstration, but it is easy to apply our theory to other platforms and tools. Figure 5 illustrates the layout of the interpreter in assembly form (FastInterpret() in interp.c). The first trunk BytecodeFetching is the code block for rescheduling and fetching, it is exactly the first part in the original source code. The second trunk LookupTable is a large lookup table used in dispatching bytecode instructions. Each entry links to a bytecode handler. It is actually the translated result of the “switch…case…case” statement. Fig. 5. The organization of the interpreter in assembly aspect The third trunk BytecodeDispatch is the aggregation of more than a hundred bytecode handlers. Most bytecode handlers are self-contained which means a bytecode handler occupies a contiguous memory space in this trunk and it does not jump to program codes stored in other trunks. There are only a few exceptions which call functions stored in other trunks, such as “invokevirtual.” Besides, there are several constant symbol tables spread over this trunk. These tables are referenced by the program codes within the BytecodeDispatch trunk. The last trunk ExceptionHandling contains code fragments related with exception handling. Each trunk occupies a number of NAND flash pages. In fact, the total size
Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory 375 of BytecodeFetching and LookupTable is about 1200 bytes (compiled with arm-elfgcc-3.4.3), which is almost small enough to fit into two or three 512-bytes-page. Figure 8 showed the size distribution of bytecode handlers. The average size of a bytecode handler is 131 bytes, and there are 79 handlers smaller than 56 bytes. In the other words, a 512-bytes-page could gather 4 to 8 bytecode handlers. The intrahandler execution flow dominates the number of cache misses generated by the interpreter. This is the reason that our approach tried to rearrange bytecode handlers within the BytecodeDispatch trunk. Fig. 6. Distribution of Bytecode Handler Size (compiled with gcc-3.4.3) 4 Analyzing Control Flow 4.1 Indirect Control Flow Graph Typical approaches derive the code placement of a program from its control flow graph (CFG). However, the CFG of a VM interpreter is a special case, its CFG is a flat spanning tree enclosed by a loop. All bytecode handlers are always sibling code blocks in the aspect of CFG regardless of executed Java applications. Therefore, the CFG does not provide information to distinguish the temporal order between each bytecode handler. If someone wants to improve the program locality by observing the dynamic execution order of program blocks, and CFG is apparently not a good tool to this end. Therefore, we proposed a concept called “Indirect Control Flow Graph” (ICFG); it uses the dynamic instruction sequence to construct the dual CFG of the interpreter. Consider a simplified virtual machine with 5 bytecode instructions: A, B, C, D, and E. Besides, take the following short alphabetic sequences as the input to the simplified virtual machine: A-B-A-B-C-D-E-C Each letter in the sequence represents a bytecode instruction. In Figure 7, the graph connected with the solid lines is the CFG of the simplified interpreter. Yet, this CFG cannot convey whether handler B will be called after handler A is executed. Therefore, we construct the ICFG by using the dashed directed lines to connect the bytecode handlers in the order of the input sequence. Actually, the Figure 8 expresses the ICFG in a readable way.
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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Architecture Enhancements for the A
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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avg normalized execution time 1.000
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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Experiences with Parallelizing a Bi
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speed-up 8 6 4 2 0 FFT3D 256 64-A F
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Normalized Cycle Count 1.00 0.90 0.
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Variation-Aware Software Techniques
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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266 P. Akl and A. Moshovos throttli
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268 P. Akl and A. Moshovos 80% 70%
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270 P. Akl and A. Moshovos 25% 20%
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272 P. Akl and A. Moshovos [4] Burg
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274 A. García et al. execution tim
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276 A. García et al. whenever LPA
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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Using Dynamic Binary Instrumentatio
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