Lecture Notes in Computer Science 4917

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256 Y. Sazeides et al. Mahlke and Natarajan [21] use static dataflow information to determine variables that may influence the outcome of a branch and then performed profiling analysis on these variable to determine simple correlation functions between the values of the variables and the branch outcome. Instructions are inserted in the code to compute the branch direction. In our view, this work also attempts to implement a variation of affectors and affectees correlation since a function supplies analogous information to what can be provided by affectee branches. A return-history-stack [22] is a method that can introduce holes in the branch history. In broad terms, a return history stack pushes in a stack the branch history register on a call and recovers it on a return, thus introducing holes in the history. A return history stack was shown to be useful for a trace predictor [22] and offered modest improvements for a direction branch predictor [23]. This suggests that there are many cases where branches executed in a function are often no significant correlators to branches executed after the function return. 6 Conclusions and Future Work In this paper we investigate the potential of selective correlation using affectors and affectees branches to improve branch prediction. Experimental analysis of affectors and affectees revealed that many branches have few correlations and often the correlations have holes between them. Prediction using selective correlation, based on oracle selection of affectors and affectees, is shown to have significant potential to improve accuracy for a both a limit and a realistic predictor. The analysis also shows that correlations past memory instruction are needed for best accuracy. Overall, our study suggests that may be worthwhile to consider the design of a realistic predictor that can exploit the properties exhibited by affectors and affectees correlation patterns by learning correlations with and without holes from long history. Another possible direction of future work, is to apply the findings of this paper to static branch prediction, and to other types of predictors, such as values and dependences. Acknowledgments. This work is partially supported by an Intel research grant. References 1. WIlkerson, C., Stark, J.: Introduction to JILP’s Special Edition for Finalists of the Championship Branch Prediction (CBP1) Competition. Journal of Instruction- Level Parallelism 7 (2005) 2. Jiménez, D.A.: The Second Championship Branch Prediction Competition. Journal of Instruction-Level Parallelism 9 (2007) 3. Seznec, A.: The Idealistic GTL Predictor. Journal of Instruction-Level Parallelism 9 (2007) 4. Evers, M., Patel, S.J., Chappel, R.S., Patt, Y.N.: An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. In: 25th International Symposium on Computer Architecture (June 1998)
The Significance of Affectors and Affectees Correlations 257 5. McFarling, S.: Combining Branch Predictors. Technical Report DEC WRL TN-36, Digital Western Research Laboratory (June 1993) 6. Thomas, R., Franklin, M., Wilkerson, C., Stark, J.: Improving Branch Prediction by Dynamic Dataflow-based Identification of Correlated Branches from a Large Global History. In: 30th International Symposium on Computer Architecture, pp. 314–323 (June 2003) 7. Jimenez, D.A., Lin, C.: Dynamic Branch Prediction with Perceptrons. In: 7th International Symposium on High Performance Computer Architecture (February 2001) 8. Burger, D., Austin, T.M., Bennett, S.: Evaluating Future Microprocessors: The SimpleScalar Tool Set. Technical Report CS-TR-96-1308, University of Wisconsin- Madison (July 1996) 9. Perelman, E., Hamerly, G., Biesbrouck, M.V., Sherwood, T., Calder, B.: Using SimPoint for Accurate and Efficient Simulation. In: International Conference on Measurement and Modeling of Computer Systems (2003) 10. Seznec, A.: The L-TAGE Branch Predictor. Journal of Instruction-Level Parallelism 9 (2007) 11. Seznec, A.: Analysis of the O-GEometric History Length branch predictor. In: 32nd International Symposium on Computer Architecture (2005) 12. Smith, J.E.: A Study of Branch Prediction Strategies. In: 8th International Symposium on Computer Architecture, pp. 135–148 (May 1981) 13. Yeh, T.Y., Patt, Y.N.: Two-Level Adaptive Branch Prediction. In: 24th International Symposium on Microarchitecture, pp. 51–61 (November 1991) 14. Juan, T., Sanjeevan, S., Navarro, J.J.: Dynamic History-Length Fitting: A third level of adaptivity for branch prediction. In: 25th International Symposium on Computer Architecture, pp. 155–166 (June 1998) 15. Michaud, P.: A PPM-like, Tag-based Predictor. Journal of Instruction-Level Parallelism 7 (2005) 16. Farcy, A., Temam, O., Espasa, R., Juan, T.: Dataflow analysis of branch mispredictions and its application to early resolution of branch outcomes. In: 31st International Symposium on Microarchitecture, pp. 59–68 (December 1998) 17. Thomas, R., Franklin, M.: Using Dataflow Based Context for Accurate Value Prediction. In: 2001 International Conference on Parallel Architectures and Compilation Techniques, pp. 107–117 (September 2001) 18. Sazeides, Y.: Dependence Based Value Prediction. Technical Report CS-TR-02-00, University of Cyprus (February 2002) 19. Constantinidis, K., Sazeides, Y.: A Hardware Based Method for Dynamically Detecting Instruction Isomorphism and its Application to Branch Prediction. In: 2nd Value Prediction Workshop (2004) 20. Chen, L., Dropsho, S., Albonesi, D.H.: Dynamic Data Dependence Tracking and its Application to Branch Prediction. In: 9th International Symposium on High Performance Computer Architecture, pp. 65–76 (February 2003) 21. Mahlke, S., Natarajan, B.: Compiler Synthesized Dynamic Branch Prediction. In: 29th International Symposium on Microarchitecture, pp. 153–164 (December 1996) 22. Jacobson, Q., Rottenberg, E., Smith, J.E.: Path-Based Next Trace Prediction. In: 30th International Symposium on Microarchitecture, pp. 14–23 (December 1997) 23. Gao, F., Sair, S.: Exploiting Intra-function Correlation with the Global History. In: Hämäläinen, T.D., Pimentel, A.D., Takala, J., Vassiliadis, S. (eds.) SAMOS 2005. LNCS, vol. 3553, Springer, Heidelberg (2005)
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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Architecture Enhancements for the A
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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References Compiler Techniques for
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Code Arrangement of Embedded Java V
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400 Author Index Shajrawi, Yousef 3
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