Lecture Notes in Computer Science 4917

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158 T.T. Hahn et al. Code size ratio (C64+/C64) no -ms 100% 95% 90% 85% 80% 75% 70% 65% 60% Reed Sol ac3 aes basicmath bitcnt blowfish des dhry21 dijkstra estone evrc g.723.1 g729 gsmAMR gsmefr jpeg modem mp3 mpeg4 tcpip wbamr zlib Fig. 7. Comparison of code size between C64x and C64+ at maximum performance Code size ratio (C64+/C64) -ms2 100% 95% 90% 85% 80% 75% 70% 65% 60% Reed Sol ac3 aes basicmath bitcnt blowfish des dhry21 dijkstra estone evrc g.723.1 g729 gsmAMR gsmefr jpeg modem mp3 mpeg4 tcpip wbamr zlib Fig. 8. Comparison of code size between C64x and C64+ at “-ms2” the figure shows, when compiling for maximum performance, the instruction set extensions yield an average 11.5 percent code size savings with no reduction in performance (points on the middle line). The points on the leftmost line indicate the performance and code size with the addition of the software pipelined loop buffer (SPLOOP). When compiling for maximum performance, the use of the instruction set extensions and the software pipelined loop buffer result in an average 17.4 percent code size reduction with no change in performance. As shown in fig. 9, the instruction set extensions create a larger code size and performance tradeoff range. When a developer’s primary desire is to control code size, this additional range can be useful in balancing performance and code size in a memory-constrained application common in embedded systems.
180% 160% 140% 120% 100% 80% 60% 40% cycles Compilation Strategies for Reducing Code Size on a VLIW Processor 159 -ms3 -ms2 -ms2 and -ms3 6400 6400+ no sploop 6400+ 20% -ms1 -ms0 no -ms -ms1 -ms0 no -ms 0% bytes -50% -40% -30% -20% -10% 0% Fig. 9. Comparison of performance and code size between C64x and C64+ at various performance and code size tradeoff levels 7 Conclusions We have presented a hybrid approach for compressing VLIW programs using a combination of compact instruction encoding and compilation techniques. The C64+ implements a unique method for encoding variable length instructions using a fetch packet header. A post-code generation tool, the compressor, ultimately selects the size of the instructions. This approach relieves the code generator of unnecessary complexity in our constrained VLIW implementation, where 32-bit instructions cannot span a 32-bit boundary and 16-bit instructions must occur in pairs. The compiler tailors a 32-bit instruction with the potential to become 16-bit depending on the code size priority selected by the user and the location and nature of the instruction. The compiler uses various techniques, including tiered register allocation and calling convention customization to tradeoff code size and performance. For a set of representative benchmarks, we presented results that showed an 11.5 percent to 23.3 percent code size reduction. Finally, the approach presented here is implemented in the C64+ processor and its production compiler. Future work includes improvements to the compiler to more effectively tailor code size optimizations for non-performance critical regions of a function.
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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Architecture Enhancements for the A
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Integrated CPU Cache Power Manageme
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Variation-Aware Software Techniques
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Average leakage-power saving (%) Va
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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Turbo-ROB: A Low Cost Checkpoint/Re
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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266 P. Akl and A. Moshovos throttli
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268 P. Akl and A. Moshovos 80% 70%
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270 P. Akl and A. Moshovos 25% 20%
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272 P. Akl and A. Moshovos [4] Burg
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274 A. García et al. execution tim
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276 A. García et al. whenever LPA
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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Complementing Missing and Inaccurat
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6.1 Filling Edge Profile from Verte
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Using Dynamic Binary Instrumentatio
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L1 D-Cache Miss Rate (%) CPI 5 4 3
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CPI Error (%) 10 5 0 -5 -10 FP Resu
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CPI Error (%) 40 30 20 10 0 Using D
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Phase Complexity Surfaces: Characte
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MLP-Aware Dynamic Cache Partitionin
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Compiler Techniques for Reducing Da
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References Compiler Techniques for
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Code Arrangement of Embedded Java V
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Aggressive Function Inlining: Preve
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foo:(80 times) BB1: Call bar BB2: C
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400 Author Index Shajrawi, Yousef 3
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