Lecture Notes in Computer Science 4917

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Albert Cohen Clark Coleman Adrian Cristal Jack Davidson Koen De Bosschere Marc Duranton Ayose Falcon Babak Falsafi Kevin Fan Paolo Faraboschi Kristian Flautner Grigori Fursin Chris Gniady Daniel Gracia-Perez Brian Greskamp Jason Hiser Wen-mei Hwu Paolo Ienne Daniel Jimenez Jose Joao Norm Jouppi Mahmut Kandemir Stefanos Kaxiras DaeHo Kim Hokyun Kim Wonsub Kim Yongjoo Kim Christos Kozyrakis Manjunath Kudlur Tushar Kumar Christopher Kung Chang Joo Lee Jongwon Lee Piotr Lesnicki Yue Li Yongmo Liang Danny Lynch Scott Mahlke Peter Marwedel Mojtaba Mehrara Avi Mendelson Rustam Miftakhutdinov Pablo Montesinos Miquel Moreto Andreas Moshovos Gilles Mouchard Veynu Narasiman Mike O’Boyle Kunle Olukotun Daniel Ortega Yunheung Paek Alex Pajuelo Santosh Pande Ioannis Papadopoulos Hyunchul Park Sanghyun Park Yale Patt Androniki Pazarloglou Maikel Pennings Antoniu Pop Alex Ramirez Lawrence Rauchwerger Organization IX John Regehr Christopher Rodrigues Shane Ryoo Esther Salami Fermin Sanchez Oliverio Santana Andre Seznec Tim Smith Guri Sohi Jaswanth Sreeram Santhosh Srinath Samuel Stone Karin Strauss M. Aater Suleman Gabriel Tanase Olivier Temam Nathan Thomas Abhishek Tiwari Josep Torrellas Sain-Zee Ueng Mateo Valero Javier Vera David Whalley Sudhakar Yalamanchili Sami Yehia Jonghee Youn Kun Zhang Hongtao Zhong
Invited Program Table of Contents Supercomputing for the Future, Supercomputing from the Past (Keynote) .................................................. 3 Mateo Valero and Jesús Labarta I Multithreaded and Multicore Processors MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing ............................................ 9 Kevin D. Kissell rMPI: Message Passing on Multicore Processors with On-Chip Interconnect ..................................................... 22 James Psota and Anant Agarwal Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE ............................ 38 Filip Blagojevic, Xizhou Feng, Kirk W. Cameron, and Dimitrios S. Nikolopoulos IIa Reconfigurable - ASIP BRAM-LUT Tradeoff on a Polymorphic DES Design ................. 55 Ricardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa, and Stamatis Vassiliadis Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array ............................................. 66 Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, and Georgi Gaydadjiev Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP ....................... 82 Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael de Nil, and Jef Van Meerbergen IIb Compiler Optimizations Fast Bounds Checking Using Debug Register ........................ 99 Tzi-cker Chiueh
Page 1 and 2: Lecture Notes in Computer Science 4
Page 3 and 4: Volume Editors Per Stenström Chalm
Page 5 and 6: VI Preface The planning of a confer
Page 7: VIII Organization Mahmut Kandemir P
Page 11: Table of Contents XIII Turbo-ROB: A
Page 14 and 15: 4 M. Valero and J. Labarta future s
Page 17 and 18: MIPS MT: A Multithreaded RISC Archi
Page 19 and 20: 2.2 VPEs as Scheduling Domains MIPS
Page 21 and 22: MIPS MT: A Multithreaded RISC Archi
Page 23 and 24: 6.1 Thread Context Virtualization M
Page 25 and 26: 8 Experimental Results MIPS MT: A M
Page 27 and 28: Cycles/ Iteration MIPS MT: A Multit
Page 29: 9 Conclusions MIPS MT: A Multithrea
Page 32 and 33: MPI: Message Passing on Multicore P
Page 38 and 39: overhead per word (cycles) 1200 100
Page 40 and 41: speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
Page 42 and 43: speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
Page 48 and 49: Modeling Multigrain Parallelism on
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Modeling Multigrain Parallelism on
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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Architecture Enhancements for the A
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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avg normalized execution time 1.000
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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180% 160% 140% 120% 100% 80% 60% 40
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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speed-up 8 6 4 2 0 FFT3D 256 64-A F
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Normalized Cycle Count 1.00 0.90 0.
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Integrated CPU Cache Power Manageme
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Variation-Aware Software Techniques
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Average leakage-power saving (%) Va
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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Turbo-ROB: A Low Cost Checkpoint/Re
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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266 P. Akl and A. Moshovos throttli
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268 P. Akl and A. Moshovos 80% 70%
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270 P. Akl and A. Moshovos 25% 20%
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272 P. Akl and A. Moshovos [4] Burg
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274 A. García et al. execution tim
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276 A. García et al. whenever LPA
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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Complementing Missing and Inaccurat
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90 100 100 25 75 25 25 100 100 10 1
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6.1 Filling Edge Profile from Verte
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Using Dynamic Binary Instrumentatio
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L1 D-Cache Miss Rate (%) CPI 5 4 3
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CPI Error (%) 10 5 0 -5 -10 FP Resu
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CPI Error (%) 40 30 20 10 0 Using D
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Phase Complexity Surfaces: Characte
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( log10) phases of Number 4.0 3.5 3
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MLP-Aware Dynamic Cache Partitionin
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(a) IPC as we vary the number of as
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Compiler Techniques for Reducing Da
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40 35 30 25 ) te ( % 20 -ra M is s
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References Compiler Techniques for
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Code Arrangement of Embedded Java V
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Aggressive Function Inlining: Preve
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f1(){ ...g();....} f2(){....q();...
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foo:(80 times) BB1: Call bar BB2: C
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400 Author Index Shajrawi, Yousef 3
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