Lecture Notes in Computer Science 4917

126 S. Eyerman, L. Eeckhout, and J.E. Smith
avg normalized execution time
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
base
tree opt
const prop/elim
basic loop opt
if-conversion
O1
O2 -fnoO2
CSE
BB reorder
strength red
recursion opt
insn scheduling
strict aliasing
alignment
adv tree opt
O2
aggr loop opt
inlining
O3
loop unrolling
software pipelining
FDO
Fig. 6. Average normalized cycle counts on a superscalar in-order processor
available in the pipeline to issue because of a branch misprediction, the cycle is assigned
to the branch misprediction cycle component.
The result of comparing the in-order processor cycle components against the out-oforder
processor cycle components is presented in Figure 4. To facilitate the discussion,
we make the following distinction in cycle components. The first group of cycle components
is affected by the dynamic instruction count and the critical path of inter-operation
dependencies; these are the base, resource stall, and branch misprediction penalty cycle
components. We observe from Figure 4 that these cycle components are affected more
by the compiler optimizations for the in-order processor than for the out-of-order processor:
14.6% versus 8.0%. The second group of cycle components are related to the
L1 and L2 cache and TLB miss events and the number of branch misprediction events.
This second group of miss events is affected more for the out-of-order processor: this
is only 2.3% for the in-order processor versus 7% for the out-of-order processor. In
other words, most of the performance gain through compiler optimizations on an inorder
processor comes from reducing the dynamic instruction count and shortening the
critical path of inter-operation dependencies. On an out-of-order processor, the dynamic
instruction count and the critical path are also important factors affecting overall performance,
however, about one half of the total performance speedup comes from secondary
effects related to I-cache, long-latency D-cache and branch misprediction behavior.
There are three reasons that support these observations. First, out-of-order execution
hides part of the inter-operation dependencies and latencies which reduces the impact
of critical path optimizations. In particular, in a balanced out-of-order processor, the
critical path of inter-operation dependencies is only visible on a branch misprediction.
Second, the base and resource stall cycle components are more significant for an inorder
processor than for an out-of-order processor; this makes the miss event cycle
components relatively less significant for an in-order processor than for an out-of-order
processor. As such, an improvement to these miss event cycle components results in
a smaller impact on overall performance for in-order processors. Third, scheduling instructions
can have a bigger impact on memory-level parallelism on an out-of-order
processor than on an in-order processor. A good static instruction schedule will place
independent long-latency D-cache and D-TLB misses closer to each other in the dynamic
instruction stream. An out-of-order processor will be able to exploit the available
MLP at run time in case the independent long-latency loads appear within a ROB size
from each other in the dynamic instruction stream. An in-order processor on the other