Lecture Notes in Computer Science 4917

204 P. Raghavan et al.
PC
(A) Unoptimized Architecture
IL1 Memory
FU FU FU FU
Centralized RF
PC
LC
Distributed
Reg. File
DL1 Cache DMA
(B) Low Power Architecture
IL1 Memory
L0 Loop Buffer1 L0 Loop Buffer2
FU FU FU
DRF1 DRF0
DL1 Scratchpad
Fig. 6. Low Power Architecture Design Space
(16 instructions deep). The register file is clustered (16 deep, 6 ports each). Both these
architectures have a standard 5 stage pipeline.
5.3 Loop Transformations
Figure 7 shows the transformations performed on the benchmark code. The first three,
loop split-loop merge-loop merge, improve data locality in memory and IPC. For the
Cortex A8 processor loop tiling is performed as an enabling transformation, vectorization
is performed manually using intrinsics. The decision on which transformations to
do is up to the designer, and defining an optimal set of transformations for a certain
platform and application domain is outside the scope of this paper.
a
Loops: b
c
*.c
WCDMA Reciever
Loop
Split
5.4 Results and Analysis
Transformations used for Arm Cortex−A8 like
a
b
a−c1
c1
b
a−c1
c2
c2
b−c2
Loop
Merge
Transformations used for TIC64x−like
Loop
Merge
Fig. 7. Transformations Used in Uruk for Optimizations
FU
Loop
Tile
To Compiler
Figure 8 shows the normalized performance in cycles for the TI C64-like processor and
the ARM Cortex A8-like processor, both before and after the transformations. The numbers
have been normalized to each processor’s initial cycle count. For the ARM, looptiling
was performed on the initial and transformed code to enable SIMD. Therefore the
gains are the result of an improvement in locality in the data memory. For the TI, the
performance gains are due to improved data locality and improved ILP. The loop-merge