Lecture Notes in Computer Science 4917

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218 N. AbouGhazaleh et al. (a) Normalized improvement in energy-delay product (b) Normalized Energy Savings (c) Performance degradation Fig. 4. Energy and delay of independent policy (Independent DVS) and our policy (Integrated DVS) relative to no-DVS policy in configuration A and two voltage domains processor
Integrated CPU Cache Power Management in Multiple Clock Domain Processors 219 Fig. 5. Average degradation in energy-delay product relative to the independent policy positive feedback cases throughout the application execution. From Table 1, we notice that the frequency of the positive feedback in adpcm, basicmath, andcrc32 is almost negligible; accordingly, there are significantly smaller benefits from our policy as shown in Figure 4. On the other hand, applications like gsm, rsynth, gcc, parser,andtwolf show high energy savings due to repeated occurrence of positive feedback cases. With respect to performance, we note that our proposed integrated policy has a slowdown of 5% on average for Mibench (7% on average for SPEC2000). This slowdown is only 1% more than the slowdown of the independent policy. To test whether a different policy that avoids the undesired positive feedback scenarios using alternative actions (specifically, different actions for rules 1 and 5 in Table 2) would perform better, we experimented with different rules for these two cases. Table 4 shows the actions of our proposed policy and seven policy variants, in addition to our proposed integrated policy P0. Figure 5 shows the average degradation in energy-delay product relative to the independent policy. It is clear that other actions for dealing with positive feedback scenarios are not as effective in reducing the energy-delay product. The degradation in energy-delay product of the policy variants ranges from 2% to 12% over our proposed policy. Table 4. Variants of our proposed policy: actions of setting the core voltage (Vc) and the cache speed (V$) in rules 1 & 5 from Table 2 rule P0 P1 P2 P3 P4 P5 P6 P7 # Vc V $ Vc V $ Vc V $ Vc V $ Vc V $ Vc V $ Vc V $ Vc V $ 1 ⇓ ⇑ ⇓ − ⇓ − ⇓ − − ⇑ − − − ⇑ − ⇑ 5 − ⇓ − ⇓ − − ⇑ − − ⇓ ⇑ − ⇑ − − − Sensitivity Analysis We study the benefit of using a domain interaction-aware DVS policy under different system configurations. We explore the state space by varying key processor configurations and the granularity of DVS control (that is, number of MCD domains). In addition to a simple embedded single-issue processor (configuration A in Table 3), we experiment with a more complex embedded processor (configuration B, the same processor
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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Experiences with Parallelizing a Bi
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272 P. Akl and A. Moshovos [4] Burg
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276 A. García et al. whenever LPA
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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Using Dynamic Binary Instrumentatio
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CPI Error (%) 10 5 0 -5 -10 FP Resu
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References Compiler Techniques for
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400 Author Index Shajrawi, Yousef 3
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