Lecture Notes in Computer Science 4917

MIPS MT: A Multithreaded RISC Architecture 13
viewtype ef_try; /* Empty/Full non-blocking poll */
viewtype pv_sync; /* PV Semaphore blocking load/store */
viewtype pv_try; /* PV Semaphore non-blocking poll */
viewtype reserved[10]; /* Reserved for future views */
} itc_cell;
For example, the ef_sync cell view provides classical blocking empty/full semantics,
such that if itc_ptr is a pointer to an itc_cell in an “empty” state, then
x = itc_ptr->ef_sync;
will cause the executing thread to be suspended until such time as some other instruction
stream performs an operation like
itc_ptr->ef_sync = y;
at which point the first thread’s x variable will pick up the value of y, and it will resume
execution.
The pv_sync view provides a more complex primitive, that of a counting, or PV semaphore[10].
Stores which reference this view cause the value of the cell to be atomically
incremented, regardless of the register value stored, while loads return the value and
perform a post-decrement if it is non-zero. If the pre-load value is zero, the load blocks
until a pv_sync store is done.
The “try” views allow for non-blocking synchronization, using either the empty/full
or the P/V paradigm. In the pv_try case, loads return the cell data value, even if zero,
performing an auto-decrement only if the pre-load value was non-zero. In the ef_try
case, loads references return zero if the cell is empty, regardless of the last data value
written, and stores may be attempted using the MIPS32 SC (store conditional) instruction,
which will indicate failure if the cell is full. Whereas the ef_sync view allows arbitrary
data to be passed through the cell, the use of a zero value to indicate the failure
of a load from an ef_try view implies that a word value of zero cannot be passed. In the
most frequent use case, however, it is pointers that are passed between threads via the
ITC cell, and a null pointers and non-pointers from an empty cell can be treated alike.
5 Hybrid Scheduling Control
Most of the study and application of multithreaded processor architecture has focused
on multithreading as a latency tolerance technique, a means of keeping fast functional
units busy in the face of long operand delays. This is of value in computationally intensive
embedded applications, but in many cases, it is the ability to provide latency avoidance,
rather than latency tolerance, where mulithreading provides an advantage in such
systems[11]. MIPS MT provides architectural support for this in several ways, allowing
processor hardware, system and application software, and external logic to jointly control
the scheduling of instruction streams.
5.1 Zero-Latency Event Service Using YIELD Instructions
The use of the YIELD instruction for thread termination was described in section 3.2
above, but the YIELD instruction is in fact a general tool for controlling the execution