Lecture Notes in Computer Science 4917

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Other Entries ... Architectural Destination Register Pervious RAT Map TROB Modify Flag (TM) ROB Pointer Architectural Destination Register Pervious RAT Map Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator 261 Reorder Buffer (ROB) Turbo-ROB (TROB) B Entries ( B � A ) A Entries Tail Pointer Head Pointer Architectural Register Bitvector (ARB) Fig. 2. Turbo-ROB organization. This figure assumes that the Turbo-ROB complements a ROB. Moreover, branch instructions occupy ROB entries but do not modify the RAT. Figure 1 illustrates via an example these two points. The branch instruction A is mispredicted and the wrong path instructions B to E are fetched and decoded before the misprediction is discovered. The ROB-only recovery mechanism traverses the ROB entries 5 to 2 in reverse order updating the RAT. However, traversing just the entries 3 and 2 is sufficient: Entry 5 contains no state information since it corresponds to a branch; entry 4 corresponding to R2 at instruction D can be ignored because the correct previous mapping (P2) is preserved by entry 2. A mechanism that exploits these observations can reduce recovery latency and hence improve performance. The TROB mechanism presented next, exploits this observation. To do so, it allows recovery only on branches and relies on the ROB or in re-execution as in [2] to handle other exceptions. 2.1 Mechanism: Structure and Operation We propose TROB, a ROB-like structure that requires fewer resources. TROB is optimized for the common case and thus allows recovery at some instructions, which we call repair points. The TROB records a subset of the information recorded in the ROB. Specifically, given a repair point B, the TROB contains at most one entry per architectural register corresponding to the first update to that register after B. Recoveries using the TROB are thus potentially faster than ROB-only recoveries. To ensure that recovery is still possible at all instructions (for handling exceptions), a normal ROB is used as a backup. Figure 2 shows that the TROB is an array of entries that are allocated and released in program order. Each entry contains an architectural register identifier and a previous RAT map. Thus, for an architecture with X architectural registers and Y physical registers, each TROB entry contains log 2X +log 2Y bits. A mechanism for associating TROB entries with the corresponding instructions R0 R1 R2 R3 Rx-1 X bits
262 P. Akl and A. Moshovos Oldest Instruction Branch Mispredicted Branch Branch 2 1 TROB Youngest Instruction ROB Oldest Instruction Branch Exception a) b) 3 Branch Youngest Instruction Fig. 3. Turbo-ROB recovery scenarios when repair points are initiated at all branches. a) Common scenario: recovery at any mispredicted branch uses only the fast Turbo- ROB. b) Infrequent scenario: recovery at any other instruction is supported using the Turbo-ROB and the ROB. is needed. In one possible implementation, each TROB entry contains a ROB pointer. Thus an extra log 2 A bits per TROB entry are needed for an architecture with an A-entry reorder buffer. Detection of the first update to each register after a repair point is performed via the help of a single “Architectural Register Bitvector” (ARB) of size equal to the number of architectural registers (X bits). A “TROB modify” (TM) bit array with as many bits as the number of ROB entries is used to track which instructions in the ROB allocated a TROB entry. This is needed to keep the TROB in a consistent state. Updating the Turbo-ROB: In our baseline design, repair points are initiated at all branches. Following a repair point, we keep track of the nearest subsequent previous RAT map for every RAT entry in the TROB. The ARB records which architectural registers have had their mapping in the RAT changed since the last repair point. The ARB is reset to all-zeros at every repair point and every time a TROB entry is created the corresponding ARB bit is set. TROB entries are created only when the corresponding ARB is zero. Finally, the corresponding TM is set, indicating that the corresponding instruction in the ROB modified the TROB. The TM facilitates in-order TROB deallocation whenever an instruction commits or is squashed. If the TROB has less entries than the ROB, it is possible to run out of free TROB entries. The base implementation stalls decode in this case. Recovery: There are two recovery scenarios with the TROB: Figure 3(a) shows the first scenario where we recover at an instruction with a repair point. RAT recovery proceeds by traversing the TROB in reverse order while updating the RAT with the previous mappings. Figure 3(b) shows the second recovery scenario where we recover at an instruction without a repair point. In the base design that allocates repair points for all branches, this scenario is not possible for branches and applies only to other exceptions. Accordingly, this will happen infrequently. We first quickly recover the RAT partially at the closest subsequent TROB repair 2 1 TROB ROB
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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Architecture Enhancements for the A
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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avg normalized execution time 1.000
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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speed-up 8 6 4 2 0 FFT3D 256 64-A F
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Normalized Cycle Count 1.00 0.90 0.
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CPI Error (%) 10 5 0 -5 -10 FP Resu
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CPI Error (%) 40 30 20 10 0 Using D
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Using Dynamic Binary Instrumentatio
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Compiler Techniques for Reducing Da
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References Compiler Techniques for
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Code Arrangement of Embedded Java V
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Aggressive Function Inlining: Preve
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400 Author Index Shajrawi, Yousef 3
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