Lecture Notes in Computer Science 4917

194 P. Raghavan et al.
optimizing applications for a given architecture, designers try to minimize the energy
consumption by improving other metrics like a reduction in the number of memory
accesses. This indirect way is however inconclusive for more complex trade-offs, like
introducing extra operations, and therefore accesses to the instruction memory, in order
to minimize accesses to the data memory. To correctly perform this type of optimizations,
an integrated energy-aware estimation flow is needed.
Decisions at different levels of abstraction have an impact on the efficiency of the
final implementation, from algorithmic level choices to source level transformations and
all the way down to micro-architectural changes. In this paper, we present an integrated
compilation and architecture exploration framework with fast performance and energy
estimation. This work enables designers to evaluate the impact of various optimizations
in terms of energy and performance. The optimizations explored can be either in the
source code, in the compiler or in the architecture.
Current embedded platforms consist of a number of processors, custom hardware and
memories. Because of increasing production costs, flexibility is getting more important
and platforms have to be used for many different and evolving products. In this work
we focus on one of the programmable processors, potentially including special purpose
Functional Units (FUs), that improve the energy efficiency for a certain application
domain. The data and instructions memory hierarchy of this processor are taken into
account.
In this context designers are facing multiple problems. Firstly, given a set of target
applications, the Instruction Set Architecture (ISA, decides on number and type of FUs),
the processor style (correct mix of instruction (ILP) and data level parallelism (DLP)),
the usage of application specific accelerator units, sizes of memories and register files
and the connectivity between these components have to be fixed. In order to reach the
required performance and energy efficiency, the retargetable tool-flow presented here
will enable a fast architecture exploration and lead to better processor designs, taking
into account all parts of the system. Our framework will correctly identify the energy
and performance bottlenecks and prevent designers from improving one part at the cost
of other parts. Since our framework allows the use of novel low power extensions for
different components of the processor, combinations of these extensions can be explored.
Secondly, after the processor has been fixed, architecture dependent software
optimizations using code transformations can dramatically improve the performance
and energy efficiency. An example of such a transformation is loop merging. This technique
can improve data locality, but can have the adverse effect of increasing register
pressure, thereby causing register spilling. Our framework will guide the designer to
choose these transformations. It directly shows the effect of software-optimizations on
the final platform metrics: cycles and Joules. Thirdly, compiler optimizations like improved
scheduling and allocation techniques can be evaluated for a range of relevant
state of the art architectures. Their effect on different parts of the system (e.g. register
files, memories and datapath components) can be tracked correctly.
Optimizing this hardware-software co-design problem is complicated by the large
size of the design space. In order to be of practical use, estimation tools should be
sufficiently fast to handle realistic application sizes. Currently, energy estimation during
processor design is done using time consuming gate level simulations. This approach