Lecture Notes in Computer Science 4917

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310 V.M. Weaver and S.A. McKee Note that gcc uses an extremely large stack. By default Qemu only emulates a 512KB stack, but the -s command-line option enables at least 8MB of stack space, which allows all gcc benchmarks to run to completion. 2.4 Valgrind Valgrind [9] is a dynamic binary instrumentation tool for the PowerPC, IA32, and AMD64 architectures. It was originally designed to detect application memory allocation errors, but it has developed into a generic and flexible DBI utility. Valgrind translates native processor code into a RISC-like intermediate code. Instrumentation occurs on this intermediate code, which is then recompiled back to the native instruction set. Translated blocks are cached. Our BBV generation code is a plugin to Valgrind 3.2.3. By default, Valgrind instruments at a super-block level rather than the basic block level. A super-block only has one entrance, but can have multiple exit points. We use the --vex-guest-chase-thresh=0 option to force Valgrind to use basic blocks, although our experiments show that using super-blocks yields similar results. Valgrind implements just-in-time translation of the program being run. We instrument every instruction to call our BBV generation routine. It would be more efficient to call only the routine once per block, but in order to work around some problems with the “rep” instruction prefix (described later) we must instrument every instruction. When calling our instruction routine, we look up the current basic block in a hash table to find a data structure that holds the relevant statistics. We increment the basic block counter and the total instruction count. If we finish an interval by overflowing the committed instruction count, we update BBV information and clear all counts. Valgrind runs from 5 (art) to 114 (vortex) times slower than native execution, making it the slowest of the tools we evaluate. 3 Evaluation To evaluate the BBV generation tools, we use the SPEC CPU2000 [15] and CPU2006 [16] benchmarks with full reference inputs. We compile the benchmarks on SuSE Linux 10.2 with gcc 4.1 and “-O2” optimization (except for vortex, which we compile without optimization because it crashes, otherwise). We link binaries statically to avoid library differences on the machines we use to gather data. The choice to use static linking is not due to tool dependencies; all three handle both dynamic and static executables. We choose IA32 as our test platform because it is widely used and because all three tools support it. We use the Perfmon2 [5] interface to gather hardware performance counter results for the platforms described in Table 1. The performance counters are set to write out the the relevant statistics every 100M instructions. The data collected are used in conjunction with simulation points and weights generated by SimPoint to calculate estimated CPI. We calculate actual CPI for the benchmarks by using the performance counter data, and use this as a basis for our error calculations. Note that calculated statistics
Using Dynamic Binary Instrumentation 311 Table 1. Machines used machine processor memory L1 I/D L2/L3 Cache performance counters used nestle 400MHz Pentium II 256MB 16KB/16KB 512KB inst retired, cpu clk unhalted spruengli 550MHz Pentium III 512MB 16KB/16KB 512KB inst retired, cpu clk unhalted itanium 800MHz Itanium 1GB 16KB/16KB 96KB/3MB ia32 inst retired, cpu cycles chocovic 1.66GHz Core Duo 1GB 32KB/32KB 1MB instructions retired, unhalted core cycles milka 1.733MHz Athlon MP 512MB 64KB/64KB 256KB retired instructions, cpu clk unhalted gallais 1.8GHz Pentium 4 256MB 12Kμ/16KB 256KB instr retired:nbogusntag, global power events:running jennifer 2GHz Athlon64 X2 1GB 64KB/64KB 512KB retired instructions, cpu clk unhalted sampaka12 2.8GHz Pentium 4 2GB 12Kμ/16KB 512KB instr retired:nbogusntag, global power events:running domori25 3.46GHz Pentium D 4GB 12Kμ/16KB 2MB instr retired:nbogusntag, global power events:running are ideal, with full warmup. If we were analyzing via a simulation, the results would likely vary in accuracy depending on how architectural state is warmed up after fast-forwarding between simulation points. We use SimPoint version 3.2, the newest version from the SimPoint website, to generate our simulation points. 3.1 The Rep Prefix When validating against actual hardware, total retired instruction counts closely match Pin results, but Qemu and Valgrind results diverge on certain benchmarks. We find the cause of this problem to be the IA32 rep prefix. This prefix appears before string instructions (which typically implement a memory operation followed by a pointer auto-increment). The prefix causes the string instruction to repeat, decrementing the ecx register until it reaches zero. A naive implementation of the rep prefix treats each repetition as a committed instruction. In actual hardware, this instruction is grouped in multiples of 4096, so only every 4096 th repetition counts as one committed instruction. The performance counters and Pin both show this behavior. Our Valgrind and Qemu plugins are modified to compensate for this, so that we achieve consistent committed instruction counts across all of the BBV generators and actual hardware. 3.2 The Art Benchmark Under Valgrind, the art floating point benchmark finishes with half the number of instructions committed by actual hardware. Valgrind uses 64-bit floating point arithmetic for portability reasons, but by default on Linux IA32, programs use 80-bit floating point operations. The art benchmark unwisely uses the “==” C operator to compare two floating point numbers, and due to rounding errors between the 80-bit and 64-bit versions, the 64-bit version can finish early, while still generating the proper reference output.
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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speed-up 8 6 4 2 0 FFT3D 256 64-A F
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Variation-Aware Software Techniques
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Average leakage-power saving (%) Va
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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400 Author Index Shajrawi, Yousef 3
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