Lecture Notes in Computer Science 4917

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foo:(80 times) BB1: Call bar BB2: CMP R3,0 JEQ BB4 BB3: ADD R3,12 BB4: RET bar:(90 times) BB5: CMP R6,R7 JEQ BB7 BB6: ADD R6,9 BB7: RET (a)Beforecodereordering Aggressive Function Inlining: Preventing Loop Blockings 393 foo:(80 times) BB1: Call bar JMP BB2 (penalty) bar: BB5: CMP R6,R7 JNE BB6 BB7: RET BB2: CMP R3,0 JNE BB3 BB4: RET BB6: ADD R6,9 JMP BB7 BB3: ADD R3,12 JMP BB4 (b) After code reordering (i) foo:(80 times) BB1: Call bar BB2: CMP R3,0 JNE BB3 BB4: RET bar: BB5: CMP R6,R7 JNE BB6 BB7: RET BB6: ADD R6,9 JMP BB7 BB3: ADD R3,12 JMP BB4 (c) After code reordering (ii) Fig. 7. Code reordering followed by function inlining foo:(80 times) BB5: CMP R6,R7 JNE BB6 BB2: CMP R3,0 JNE BB3 BB4: RET BB6: ADD R6,9 JMP BB4 BB3: ADD R3,12 JMP BB4 bar:(10 times) BB5: CMP R6,R7 JEQ BB7 BB6: ADD R6,9 BB7: RET (d) After reordering and inlining grouping increases the Icache miss rate by spreading the hot code over more cache lines. In addition it increases the amount of “mixed” Icache lines containing both hot and cold instructions. Thus, after inlining we apply code reordering to rearrange the code layout by grouping hot consecutive basic blocks into consecutive chains. Code reordering is the last phase of the optimization process and as such it can determine the final location of instructions. Hence, code reordering can rearrange code segments such that Icache misses are reduced. Most previous works also used code reordering after inlining as will be explained in section 5, hence this aspect of code reordering is well known. In this section we focus on a different aspect of code reordering and inlining which is the way inlining can help improve code reordering’s ability to group larger and more efficient code segments. The code reordering algorithm for generating optimized sequences of basic blocks is based on the tracing scheme [11]. The algorithm starts with an entry point and grows a trace of basic blocks, based on profile information. A trace is a sequence of basic blocks that are executed serially. When the control flow to the next block in a trace reaches an indirect branch instruction (which usually indicates a function return) or falls below a certain frequency threshold, the algorithm stops growing a trace and starts a new one. The example in Figure 7 exemplifies this scenario (hot basic blocks are boldfaced). Figure 7a shows the hot path within function foo that includes a hot call to function bar. There are two options to build the traces during code reordering:
394 Y. Ben Asher et al. 1. Ideally, the best reordering trace starts with the hot basic block BB1 in foo, followed by the hot basic blocks BB5 and BB7 in bar itself, and finally the hot basic blocks BB2 and BB4 that follow the call instruction to bar in foo. This trace reordering is given in Figure 7b. Unfortunately, although this is the ideal reordering trace, there is an extra jump instruction to BB2 that we are forced to add immediately after the call instruction to bar. Theextra jump instruction is necessary to maintain the original program correctness, so that the return instruction in bar will continue to BB2. 2. In order to avoid the extra jump instruction, it is possible to form two reordering traces. A trace consisting of the hot basic blocks in foo: BB1,BB2, and BB4, is followed by a second trace consisting of the hot basic blocks in bar: BB5 and BB7. The resulting code for this selection of reordering traces is shown in Figure 7c. Although this selection does not generate extra jumps for maintaining correctness, it does not reflect the true control flow of the program, as it avoids creating traces that can cross function boundaries. Figure 7 shows that after inlining bar at the call site in foo, the code reordering creates the optimal hot path without the extra jump or return instructions, and by following the true control flow. Furthermore, function inlining increases the average size of each reordering trace. In Figure 7, the reordering trace size after function inlining includes six instructions, which is longer than each of the reordering traces BB1,BB2,BB3 or BB5,BB7, shown in Figure 7c. The longer the traces produced by code reordering, the better the program locality. We assert that the average size of traces created before aggressive inlining vs. the average size after inlining can serve as a measure for the improvement to the reverse effect where inline helps code reordering. In general, the average size of traces increases due to function inlining: traces that started to grow in a certain function can now grow into the corresponding inlined callee functions. 4.1 Synergy Experimental Results The following experimental results demonstrate this “reverse effect” and synergy between function inlining and code reordering on the Power4. The Power4 has an extensive set of Performance Counters (PMCs), that enable us to isolate the reasons for a program’s behavior. These count the L1 Icache fetches and branch target mispredictions. Figure 8 shows the improvements of reduced L1 Icache fetches (percentage) comparing code reordering and the combination of inlining and code reordering (denoted as “aggressive inlining”). The average improvement due to inlining is from 16% to 24%. More significant results are presented in Figure 9, which shows the percentage of reduced branch target mispredictions. The code ordering scheme adds extra branches, which cause extra target mispredictions. Applying the aggressive inlining scheme removes many of these branches and reduces the number of target mispredictions for most applications. The direction mispredictions are reduced as well, albeit at a lower rate (3%) than the target mispredictions. We have also tested the synergy between code reordering and inlining on the PowerPC 405 processor used for embedded systems. The PowerPC 405 is the core
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Lecture Notes in Computer Science 4
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Volume Editors Per Stenström Chalm
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VI Preface The planning of a confer
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VIII Organization Mahmut Kandemir P
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Invited Program Table of Contents S
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Table of Contents XIII Turbo-ROB: A
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4 M. Valero and J. Labarta future s
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MIPS MT: A Multithreaded RISC Archi
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2.2 VPEs as Scheduling Domains MIPS
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MIPS MT: A Multithreaded RISC Archi
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6.1 Thread Context Virtualization M
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8 Experimental Results MIPS MT: A M
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Cycles/ Iteration MIPS MT: A Multit
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9 Conclusions MIPS MT: A Multithrea
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MPI: Message Passing on Multicore P
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overhead per word (cycles) 1200 100
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speedup 3.5 3 2.5 2 1.5 1 0.5 0 rMP
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speedup 9 8 7 6 5 4 3 2 1 0 rMPI: M
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Modeling Multigrain Parallelism on
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BRAM-LUT Tradeoff on a Polymorphic
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32 L0 L1 BRAM-LUT Tradeoff on a Pol
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Implementation of an UWB Impulse-Ra
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Fast Bounds Checking Using Debug Re
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Studying Compiler Optimizations on
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CLI as an Effective Deployment Form
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Compilation Strategies for Reducing
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Experiences with Parallelizing a Bi
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Drug Design Issues on the Cell BE 1
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COFFEE: COmpiler Framework for Ener
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Benchmark Source Code * transformed
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RTL for each Component * Gate−lev
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Integrated CPU Cache Power Manageme
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Variation-Aware Software Techniques
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244 Y. Sazeides et al. of mispredic
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246 Y. Sazeides et al. Affector BB1
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248 Y. Sazeides et al. 2.3 How to U
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250 Y. Sazeides et al. Cumulative D
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252 Y. Sazeides et al. ijpeg, andbo
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254 Y. Sazeides et al. Misses/KI 12
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256 Y. Sazeides et al. Mahlke and N
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Turbo-ROB: A Low Cost Checkpoint/Re
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260 P. Akl and A. Moshovos Original
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262 P. Akl and A. Moshovos Oldest I
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264 P. Akl and A. Moshovos new firs
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268 P. Akl and A. Moshovos 80% 70%
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272 P. Akl and A. Moshovos [4] Burg
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274 A. García et al. execution tim
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278 A. García et al. @12: load r2,
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280 A. García et al. Target Loop E
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282 A. García et al. reduction 100
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284 A. García et al. IPC speedup 7
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286 A. García et al. SPECfp benchm
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Complementing Missing and Inaccurat
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Using Dynamic Binary Instrumentatio
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Page 406: 400 Author Index Shajrawi, Yousef 3
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