Lecture Notes in Computer Science 4917

198 P. Raghavan et al.
Instruction Memory Hierarchy (IMH). A traditional instruction memory is activated
every cycle to fetch new instructions. Especially in wide architectures, like VLIWs, this
can be one of the most energy consuming parts of the system. Design space exploration
of the IMH can therefore have a large overall effect on the processor energy efficiency.
The IMH can be simulated as a cache, a scratchpad or a multi-level hierarchy. Other
advanced features, like L0 clustering and loop counters (e.g. [7,8]), are also supported.
Loop buffers are commonly used in state of the art processors, like [9,10]. Loop buffers
are small memories which contains the instructions for one nested loop. They reduce
the energy consumption of the IMH by exploiting the locality when executing loops. A
loop controller (LC) iterates over the instructions of the loop in the buffer.
Figure 2 shows different supported configurations of the instruction memory. Figure
2(a) is a conventional L1 configuration where the Program Counter (PC) fetches instructions
from the L1 instruction cache and executes them on the FUs. Figure 2(b) shows
a centralized loop buffer, where the loops are loaded from the L1 instruction memory
to the loop buffer when the loop starts. During the loop execution, the LC (Loop Controller)
fetches the instructions from the loop buffer instead of the L1 memory. Figure
2(c) shows a distributed loop buffers that can been customized to the application loop
size for every slot to minimize energy consumption, but are still controlled by a single
LC. The COFFEE framework supports automatic identification and loading of loops into
the loop buffers. Compilation and design space exploration for distributed loop buffers
is described in detail in [8,11]. More complex loop buffer organizations, where every
loop buffer is controlled by a separate LC [12], are also supported, but a description of
this concept is outside the scope of this paper. For all these cases, compilation, simulation
and energy estimation are supported.
PC
(a) Regular L1 Instr. Memory (b) Centralized Loop Buffer based Memory (c) Distributed Loop Buffer based Memory
IL1 Memory
FU FU FU FU
PC
LC
IL1 Memory
FU FU FU FU
PC
IL1 Memory
L0 Loop Buffer LC L0 Loop Buffer1 L0 Loop Buffer2
FU FU FU FU
Fig. 2. Variants of Instruction Memory Configuration are supported in Coffee
3.2 Processor Core Subsystem
The processor core subsystem consists of the datapath units and register file. These
components are described below:
Processor Datapath. Our flow supports a large datapath design space. Different styles
of embedded processors can be modeled, from small RISC processors with a single slot,
to wide VLIW processors with many heterogeneous execution slots. Multiple slots can
execute instructions in parallel, and can internally consist of multiple functional units
that execute mutually exclusively. The number of slots and the instructions that can be